參數(shù)資料
型號(hào)： μPD4564441
廠商： NEC Corp.
英文描述： 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
中文描述： 6400位同步DRAM（6400同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 12/84頁(yè)
文件大?。?/td> 697K
代理商： ΜPD4564441
12
μ
PD4564441, 4564841, 4564163 for Rev. E
Fig.4
Column address and write
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Col.
Fig.5
Column address and read
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Col.
Fig.6
Auto refresh command
Add
A10
A12, A13
(Bank select)
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst write
operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column
address.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR refresh operation. The
refresh address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
During t
RC
period (from refresh command to refresh or activate
command), the
μ
PD4564xxx cannot accept any other command.
相關(guān)PDF資料
PDF描述
μPD4564841 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564323 64M-bit Synchronous DRAM(64M 同步動(dòng)態(tài)RAM)
μPD45D128164 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
μPD45D128442 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
μPD45D128842 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
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