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參數(shù)資料
| 型號： | μPD4516421A |
| 廠商： | NEC Corp. |
| 英文描述： | 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM) |
| 中文描述： | 1,600位同步DRAM（1,600同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 21/86頁 |
| 文件大?。?/td> | 904K |
| 代理商： | ΜPD4516421A |
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μ
PD4516421A, 4516821A, 4516161A for Rev. P
21
2.
State abbreviations
I = Idle
A = Row active
R = Read with No precharge (No precharge is posted)
W = Write with No precharge (No precharge is posted)
RP = Read with auto precharge (Precharge is posted)
WP = Write with auto precharge (Precharge is posted)
Any = Any State
X0Y1 = Y1X0 = Bank A is in state “X”, Bank B is in state “Y”
(X/Y)0Z1 = Z1(X/Y)0 = Bank A is in state “X” or “Y”, Bank B is in state “Z”
3.
If the
μ
PD4516
×××
A is in a state other than above listed in the “From State” column, the command is illegal.
4.
The states listed under “To” might not be entered on the next clock cycle.
Timing restrictions apply.
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100-
μ
s or longer pause must precede any signal toggling.
(2) After the pause, both banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum t
RP
is satisfied, the mode register can be programmed.
After the mode register set cycle, t
RSC
(2CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1.
The sequence of Mode register programming and Refresh above may be transposed.
2.
CKE and DQM must be held high until the Precharge command is issued to ensure data bus Hi-Z.
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