參數(shù)資料
型號： μPD4516421A
廠商： NEC Corp.
英文描述： 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
中文描述： 1,600位同步DRAM（1,600同步動態(tài)RAM）的
文件頁數(shù)： 12/86頁
文件大小： 904K
代理商： ΜPD4516421A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
12
Write command
(CS, CAS, WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst write
operation. The first write data in burst can be input with this command with
subsequent data on following clocks.
Read command
(CS, CAS = Low, RAS, WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
(CS, RAS, CAS= Low, WE, CKE = High)
This command is a request to begin the CBR refresh operation. The
refresh address is generated internally.
Before executing CBR refresh, both banks must be precharged.
After this cycle, both banks will be in the idle (precharged) state and
ready for a row activate command.
During t
RC
period (from refresh command to refresh or activate command),
the
μ
PD4516
×××
A cannot accept any other command.
Fig. 4 Column address and
write command
Add
A10
WE
CAS
RAS
CS
CKE
CLK
H
(Bank select)
Col.
Fig. 5 Column address and
read command
Add
A10
WE
CAS
RAS
CS
CKE
CLK
H
(Bank select)
Col.
Fig. 6 Auto refresh command
Add
A10
WE
CAS
RAS
CS
CKE
CLK
H
(Bank select)
相關(guān)PDF資料
PDF描述
μPD4516821A 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
μPD45256163 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
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