參數(shù)資料
型號: μPD4516161A
廠商: NEC Corp.
英文描述: 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
中文描述: 1,600位同步DRAM(1,600同步動態(tài)RAM)的
文件頁數(shù): 34/86頁
文件大?。?/td> 904K
代理商: ΜPD4516161A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
34
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
When CAS latency is 2, the write data written prior to the precharge command will be correctly stored.
However, invalid data may be written at the same clock as the precharge command. To prevent this from happening,
DQM must be high at the same clock as the precharge command. This will mask the invalid data.
Write
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, CAS latency = 2
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D4
D5
(t
RAS
must be satisfied)
When CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must
be high at the same clock as the precharge command. This will mask the invalid data.
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst length = X, CAS latency = 3
CLK
DQ
Command
DQM
t
RP
Hi-Z
(t
RAS
must be satisfied)
Write
PRE
ACT
D1
D2
D3
D4
D5
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