參數(shù)資料
型號(hào)： μPD4516161A
廠商： NEC Corp.
英文描述： 16M-bit Synchronous DRAM(16M 同步動(dòng)態(tài)RAM)
中文描述： 1,600位同步DRAM（1,600同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 26/86頁(yè)
文件大?。?/td> 904K
代理商： ΜPD4516161A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
26
9. Precharge
The precharge command can be issued anytime after t
RAS(MIN.)
is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after t
RP
is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst
is as follows.
CAS latency = 2: One clock earlier than the last read data.
CAS latency = 3: Two clocks earlier than the last read data.
T0
T1
T2
T3
T4
T5
T6
T7
Burst length = 4
Read
Read
Q1
Q2
Q3
Q4
PRE
Hi-Z
Q1
Q2
Q3
Q4
PRE
Hi-Z
(t
RAS
must be satisfied)
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
In order to write all data to the memory cell correctly, the asynchronous parameter “t
DPL
“ must be satisfied. The
t
DPL(MIN.)
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks
are calculated by dividing t
DPL (MIN.)
with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word
is valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS latency
Read
Write
2
–1
+t
DPL (MIN.)
3
–2
+t
DPL (MIN.)
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