參數(shù)資料
型號(hào)： μPD4516161A
廠商： NEC Corp.
英文描述： 16M-bit Synchronous DRAM(16M 同步動(dòng)態(tài)RAM)
中文描述： 1,600位同步DRAM（1,600同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 10/86頁
文件大?。?/td> 904K
代理商： ΜPD4516161A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
10
1. Input/Output Pin Function
Pin name
Input/Output
Function
CLK
Input
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal
clock is not issued and the
μ
PD4516
×××
A suspends operation.
When the
μ
PD4516
×××
A is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
CS
Input
CS low starts the command input cycle. When CS is high, commands are ignored
but operations continue.
RAS, CAS, WE
Input
RAS, CAS and WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
A0 - A11
Input
Row Address is determined by A0 - A10 at the CLK (clock) rising edge in the
activate command cycle. It does not depend on the bit organization.
Column Address is determined by A0 - A9 at the CLK rising edge in the read or write
command cycle. It depends on the bit organization: A0 - A9 for
×
4 device, A0 - A8
for
×
8 device and A0 - A7 for
×
16 device.
A11 is the bank select signal (BS). In command cycle, A11 low selects bank A and
A11 high selects bank B.
A10 defines the precharge mode. When A10 is high in the precharge command
cycle, both banks are precharged; when A10 is low, only the bank selected by A11
is precharged.
When A10 high in read or write command cycle, the precharge start automatically
after the burst access.
DQM
UDQM
LDQM
Input
DQM controls I/O buffers. In
×
16 products, UDQM and LDQM control upper
byte and lower byte I/O buffers, respectively.
In read mode, DQM controls the output buffers like a conventional OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory
cell if DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ15
Input/Output
DQ pins have the same function as I/O pins on a conventional DRAM.
V
CC
V
SS
V
CC
Q
V
SS
Q
(Power supply)
V
CC
and V
SS
are power supply pins for internal circuits. V
CC
Q and V
SS
Q are power
supply pins for the output buffers.
相關(guān)PDF資料
PDF描述
μPD4516421A 16M-bit Synchronous DRAM(16M 同步動(dòng)態(tài)RAM)
μPD4516821A 16M-bit Synchronous DRAM(16M 同步動(dòng)態(tài)RAM)
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