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參數(shù)資料
| 型號： | μPD42280 |
| 廠商： | NEC Corp. |
| 英文描述： | 2 M-Bit Field Buffer(2M位現(xiàn)場緩存) |
| 中文描述： | 2 m位場緩沖器（200萬位現(xiàn)場緩存） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ΜPD42280 |
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6
μ
PD42280
3.
MEMORY OPERATION
3.1
Write Operation
When WE input is in low level, the data input to DI0 to DI7 is written into the write data register every 8 bits together
synchronizing with WCK input.
The write data should be input to meet the setup time and the hold time for the back rise up edge of WCK input
cycle.
When WE input is attained to a high level, the write operation is prohibited. The write address pointer is stopped
at the position of high level input state. When the low level is input again, the operation is started from the stopped
address.
Though the write operation is prohibited at any time, WE signal should be input to meet the set up time and the
hold time for the rise up edge of WCK.
3.2
Read Operation
When RE input and OE input are in low level, the data is output to DO0 to DO7 from the read data register every
8 bits together synchronizing with RCK input.
The read data is output after access time (t
AC
) from the rise up edge of RCK input cycle.
When RE input is attained to a high level, the read address pointer is stopped at the position of the high level input
state. When inputting a low level again, the operation is started from the stopped address.
When OE input is attained to a high level, the output will be a high impedance. The content of the read address
pointer increases synchronously with RCK input, not depending on the input level of OE signal.
Though the read operation can be prohibited at any time, RE signal/OE signal should be input to meet the setup
time and hold time for the rise up edge of RCK.
When the new data is read, the write address should be preceded 200 to 262, 223 or less cycles than the read
address.
When the old data is read, the difference between the write address and the read address should be 0 cycle (the
read address and the write address are the same).
When the read address and the write address compete with each other by double speed conversion etc. in the same
field, in the data of the last 192 words the old data (the data prior to 1 field) may be output.
3.3
Reset Operation
The reset signal can be input any time, without depending on WE, RE and OE signals. WRST and RRST signals
should be input to meet the setup time and the hold time for the rise up edge of WCK, RCK inputs. When the reset
signal is input in disable cycles, the reset operation is executed after the disable cycles.
The output and input of data are possible from the cycle (0 address) where low level is input to WRST, RRST.
3.4
Initialize
Following initializing should be taken when the power supply is ON.
(1) Stand-by period should be taken more than 100
μ
s.
(2) WRST and RRST signals should be input for initializing of the write address and read address.
(3) More than 82 dummy cycles should be taken where low level is input to RE and WE.
(4) Ordinary operation is executed after next low level is input to WRST and RRST.
Remark
New data : Data written latest,
Old data : Stored data just before write operation
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