參數(shù)資料
型號(hào): μPD42280
廠商: NEC Corp.
英文描述: 2 M-Bit Field Buffer(2M位現(xiàn)場(chǎng)緩存)
中文描述: 2 m位場(chǎng)緩沖器(200萬(wàn)位現(xiàn)場(chǎng)緩存)
文件頁(yè)數(shù): 12/28頁(yè)
文件大?。?/td> 200K
代理商: ΜPD42280
12
μ
PD42280
(3) After write is started by inputting a low-level WRST signal, input the next low-level WRST signal 82 or more
addresses apart.
Although this is highly improbable in actual practice, if no reset is executed but the operation transits from address
262,223 to address 0, this will be interpreted as a reset.
(4) After read is started by inputting a low-level RRST signal, input the next low-level RRST signal 82 or more
addresses apart.
At the same time as (3) above, if no reset is executed but the operation transits from address 262,223 to address
0, this will be interpreted as a reset.
(5) Do not raise the RE signal from low level to high level at address 0 or during a reset cycle.
This is a restriction particular to internal device operation. Be sure not to perform the operation described in Figure
4-2.
Figure 4-2 Violation of Restriction (5)
RCK
RRST
RE
Cycle n
Cycle n + 1
Reset cycle
Rising edge of RE signal
occurs during reset cycle
Thus it can be seen that due to restriction (5), it is not possible to use RE to stop the read address at address
0 using RE.
To stop the read address at address 0, continue inputting low levels to RRST. However, in this case, the data
of address 0 is newly output each time RCK is input. Therefore, when new data is written to address 0 on the
write side, and the written data becomes readable, new data is read.
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