參數(shù)資料
型號(hào)： μPD42280
廠商： NEC Corp.
英文描述： 2 M-Bit Field Buffer(2M位現(xiàn)場(chǎng)緩存)
中文描述： 2 m位場(chǎng)緩沖器（200萬(wàn)位現(xiàn)場(chǎng)緩存）
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 200K
代理商： ΜPD42280
5
μ
PD42280
2.
EXPLANATION FOR THE MEMORY AND FUNCTION BLOCK
2.1
Memory Cell Array
This is a memory cell array in this product consisting of dynamic memory cells, with 256K
×
8 (2M bit) configuration.
2.2
Input Buffer
This is a buffer to input the signals of DI0 to DI7 to the write data register or SRAM buffer.
2.3
Output Buffer
This is a buffer to output the data from the read data register or SRAM buffer to DO0 to DI7.
2.4
Write Data Register/Write Address Pointer
This is a register to temporarily store the data input to DI0 to DI7.
The input data is stored in the address directed
by the write address pointer. In the write address pointer, its content increases every WCK input. When the write data
register is filled with data, the data are transferred to the memory cell array together, and the write address pointer
is reset to the 0 address. The data are transferred by 64 words unit.
2.5
Read Data Register/Read Address Pointer
This is a register to temporarily store the data transferred together from the memory cell array. The data in the
register directed by the read address pointer is output to DO0 to DO7. In the read address pointer, its content increases
every RCK input. When the read data register is emptied, the data read from the memory cell array is transferred
together to the register, and the read address pointer is reset to the 0 address. The data are transferred by 64 words
unit.
2.6
SRAM Buffer
This is a buffer to store the data for 80 words after the write address is reset by WRST. Also, when a read address
is reset by the input of RRST signals, the data for 80 words after the reset is output (to DO0 to DO7) from SRAM buffer.
2.7
Write Address Counter
This is a counter to direct the row address of the write data. When the data is transferred to memory cell array from
the write data register, the content of the counter increases. When input of the last address is attained, the content
of the counter is reset to the 0 address.
2.8
Read Address Counter
This is a counter to direct the row address of the read data. When the data is transferred to the read data register
from memory cell array, the content of the counter increases. When input of RRST signals or the last address is
attained, the content of the counter is reset to the 0 address.
2.9
Refresh Address Counter/Refresh Timer
This is a counter to direct the refresh address. Its content is increased one by one by the refresh timer. Because
self refresh function is incorporated, the refresh operation is executed automatically.
2.10
Address Selector
This is a selector which selects one of the addresses directed by the address counter, read address counter and
refresh address counter as the row address of memory cell array.
2.11
Controller/Timing Generator
Each block is controlled by the control signals from the input pins of this block.
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