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參數(shù)資料
| 型號： | Z90T361PZ016SC |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 19/187頁 |
| 文件大?。?/td> | 2235K |
| 代理商： | Z90T361PZ016SC |
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
PS005901-1100
11
External Registers
The Z90T366 module is capable of accessing eight external registers directly
using only the three external register address signals that are normally available.
Two user bits (Status register S6-S5) are combined with the register address
signals to provide the ability to address four banks of eight registers each. The
registers most critical for speed are located together in Bank 3. In this
specification, all external registers are referred to
RX(Y)<Z>
where:
X
Y
Z
is a register number within a register bank;
is a bank number; and
is a bit field number
An external register bank can be selected by setting bits 6 and 5 in the status
register to define the bank, then specifying the address of the register on the
external register address bus.
External registers reside on the chip and are used to control the operation of all
the peripheral modules in the device. By reading or writing to the fields in the
external registers, the user can interact with the peripheral devices on the chip.
Virtual Registers
BUS
Bus. It is a virtual register. (Physical RAM does not exist on the chip.)
is a read-only register that, when accessed, returns the contents of the D-
Dn:b
used as pointers to locations in program memory. The programmer decides which
location to choose two bits from in the status register and which two bits in the
operand. This means only the lower 16 possible locations in RAM can be
specified. At any one time there are eight usable pointers, four per bank, and the
four pointers are in consecutive locations in RAM.
These eight data pointers refer to possible locations in RAM that can be
For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refers
to locations 4/5/6/7 in RAM bank 0.
Note:
When the data pointers are being written to, a number is
actually being loaded to Data RAM, so they can be used as a
limited method for writing to RAM.
Additional Control Registers (AR)
Additional Control Registers (AR) control new peripheral blocks like palette banks
and memory management. To activate ARs, R0(1)<b> must be set to “1.” ARs can
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參數(shù)描述 |
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