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參數(shù)資料
| 型號： | Z9104CAB |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):8A; Peak Non Repetitive Surge Current, Itsm:100A; Gate Trigger Current Max, Igt:15uA |
| 中文描述： | 六分布式輸出時鐘驅(qū)動器| TQFP封裝| 32腳|塑料 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 69K |
| 代理商： | Z9104CAB |
Variable Delay Motherboard Clock Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07083 Rev. *A
5/07/2001
Page 1 of 8
Z9104
APPROVED PRODUCT
Product Features
Output phase relationship is precisely controllable
with respect to input clock via a dedicated external
feedback path.
2K volts ESD protected
6 Low Skew Clocks Generated
One 2.5 Volt output clock
Outputs are individually enabled.
Output frequencies from 30 to 100 MHz.
3.3 Volt Vdd operation
Synchronous output enable and disable control
45 - 55% output duty cycle
+/- 100 pSec Cycle to Cycle Jitter
32-Lead TQFP package
Block Diagram
Ncounter
FBS0
FBS1
Stop
Logic
1
0
Stop
Logic
Stop
Logic
Stop
Logic
Stop
Logic
Pcounter
SC25
SC2,3
SC4
SC5
SC6
CLK6
CLK5
CLK4
CLK3
CLK25
PLL
REFIN
FBIN
FBOUT
PLLEN
MODE
VDDF
OEALL
STOPCLK
CLK2
VDD25
VDD
Feedback Scale Select Codes
Mode
FBS1
FBS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
*Multiplication Factor – The multiplication factor for
these configurations is the output frequency with
respect to REFIN (FOUT=FIN X multiplication factor)
Pcounter
÷
4
÷
4
÷
4
÷
8
÷
4
÷
4
÷
4
÷
8
Ncounter
÷
8
÷
10
÷
12
÷
12
÷
4
÷
5
÷
6
÷
8
MF*
2.0
2.5
3.0
1.5
1.0
1.25
1.5
1.0
Pin Configuration
Z9104
V
M
S
S
V
C
V
C
V
S
S
S
F
V
F
V
VSS
CLK3
VDD
CLK4
VSS
CLK5
VDD
CLK6
VDDI
REFIN
PLLEN
FBS0
FBS1
OEALL
STOPCLK
VSSI
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
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