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參數(shù)資料
| 型號(hào)： | Z86L9808SSC |
| 英文描述： | Triac; Triac Type:Internally Triggered; Peak Repetitive Off-State Voltage, Vdrm:600V; On-State RMS Current, IT(rms):10A; Gate Trigger Current (QI), Igt:25uA; Package/Case:TO-220; Gate Trigger Current Max, Igt:1.5A |
| 中文描述： | 單片機(jī)| 8位| Z8的CPU |的CMOS |?？苵 28腳|塑料 |
| 文件頁數(shù)： | 66/87頁 |
| 文件大?。?/td> | 1182K |
| 代理商： | Z86L9808SSC |
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Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
PS006403-0502
60
Watch-Dog Timer Mode Register (WDTMR)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its termi-
nal count. The WDT must initially be enabled by executing the WDT instruction.
On subsequent executions of the WDT instruction, the WDT is refreshed. The
WDT circuit is driven by an on-board RC oscillator or external oscillator from the
XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V)
flags.
The POR clock source is selected with bit 4 of the WDT register. Bit 0 and 1 con-
trol a tap circuit that determines the minimum time-out period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 8). This register is accessible only
during the first 61 processor cycles (122 XTAL clocks) from the execution of the
first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode
Recovery (Figure 33). After this point, the register cannot be modified by any
means (intentional or otherwise). The WDTMR cannot be read. The register is
located in Bank F of the Expanded Register Group at address location
0Fh
. It is
organized as shown in Figure 33.
WDTMR (0F) 0F
Figure 33. Watch-Dog Timer Mode Register (Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
WDT TAP INT RC OSC
00
5 ms min
01*
10 ms min
10
20 ms min
11
80 ms min
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
Reserved (Must be 0)
Reserved (Must be 0)
* Default setting after reset
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PDF描述 |
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