參數(shù)資料
型號(hào): Z86L9808SSC
英文描述: Triac; Triac Type:Internally Triggered; Peak Repetitive Off-State Voltage, Vdrm:600V; On-State RMS Current, IT(rms):10A; Gate Trigger Current (QI), Igt:25uA; Package/Case:TO-220; Gate Trigger Current Max, Igt:1.5A
中文描述: 單片機(jī)| 8位| Z8的CPU |的CMOS |??苵 28腳|塑料
文件頁(yè)數(shù): 60/87頁(yè)
文件大?。?/td> 1182K
代理商: Z86L9808SSC
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
PS006403-0502
54
PCON (FH) 00H
Figure 28. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the compar-
ator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configu-
ration.
Port0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop-
Mode Recovery (Figure 29). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input is required from the recovery source. Bit 5 controls the reset delay after
recovery. Bits D2, D3, and D4, or the SMR register, specify the source of the Stop-
Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not.
The SMR is located in Bank F of the Expanded Register Group at address
0Bh
.
D7
D6
D5
D4
D3
D2
D1
D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 0
0: Open-Drain
1: Push-Pull
Reserved (Must be 1)
* Default setting after reset
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