參數(shù)資料
型號： XRT94L31_07
廠商： Exar Corporation
英文描述： 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
中文描述： 3通道DS3/E3/STS-1給STS-3/STM-1映射器集成電路
文件頁數(shù)： 131/133頁
文件大?。?/td> 1014K
代理商： XRT94L31_07
XRT94L31
II
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
1.3.5 INGRESS TIMING FOR STS-1/STM-0 APPLICATIONS............................................................................................ 112
T
ABLE
13: T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
STS-1/STM-0 A
PPLICATIONS
(
RISING
EDGE
OF
DS3/E3/STS_1_CLOCK_IN) ..................................................................................................................................... 112
T
ABLE
14: T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
STS-1/STM-0 A
PPLICATIONS
(
FALLING
EDGE
OF
DS3/E3/STS_1_CLOCK_IN) ..................................................................................................................................... 112
1.3.6 THE EGRESS DS3/E3/STS-1 INTERFACE TIMING................................................................................................. 112
F
IGURE
17. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
DS3/E3/STS-1
SIGNALS
THAT
ARE
OUTPUT
FROM
THE
DS3/E3/STS-1 LIU I
N
-
TERFACE
(
IN
THE
R
ECEIVE
/E
GRESS
D
IRECTION
)........................................................................................................... 113
1.3.7 EGRESS TIMING FOR DS3/E3 APPLICATIONS....................................................................................................... 113
T
ABLE
15: T
IMING
I
NFORMATION
FOR
THE
E
GRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
DS3/E3 A
PPLICATIONS
(
RISING
EDGE
OF
DS3/E3/
STS_1_CLOCK_OUT) .............................................................................................................................................. 113
T
ABLE
16: T
IMING
I
NFORMATION
FOR
THE
E
GRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
DS3/E3 A
PPLICATIONS
(
FALLING
EDGE
OF
DS3/E3/
STS_1_CLOCK_OUT) .............................................................................................................................................. 113
1.3.8 EGRESS TIMING FOR STS-1/STM-0 APPLICATIONS............................................................................................. 113
T
ABLE
17: T
IMING
I
NFORMATION
FOR
THE
E
GRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
STS-1/STM-0 A
PPLICATIONS
A
PPLICATIONS
(
RISING
EDGE
OF
DS3/E3/STS_1_CLOCK_OUT) ................................................................................................................... 114
1.3.9 EGRESS TIMING FOR STS-1/STM-0 APPLICATIONS (CONTINUED).................................................................... 114
T
ABLE
18: T
IMING
I
NFORMATION
FOR
THE
E
GRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
STS-1/STM-0 A
PPLICATIONS
A
PPLICATIONS
(
FALL
-
ING
EDGE
OF
DS3/E3/STS_1_CLOCK_OUT) ............................................................................................................. 114
1.4 STS-1/STM-0 TELECOM BUS INTERFACE TIMING INFORMATION........................................................... 114
1.4.1 SOME NOTES ABOUT THE STS-1/STM-0 TELECOM BUS INTERFACE............................................................... 114
1.4.2 THE RECEIVE STS-1/STM-0 TELECOM BUS INTERFACE TIMING........................................................................ 114
F
IGURE
18. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
R
ECEIVE
STS-1/STM-0 T
ELECOM
B
US
I
NTERFACE
.................................................................................................................................................................. 115
T
ABLE
19: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STS-1/STM-0 T
ELECOM
B
US
I
NTERFACE
....................................................... 115
1.4.3 THE RECEIVE STS-1/STM-0 TELECOM BUS INTERFACE TIMING (FOR CHANNEL 0 WHEN CONFIGURED TO OP-
ERATE IN THE STS-3/STM-1 MODE)......................................................................................................................... 115
F
IGURE
19. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
R
ECEIVE
STS-1/STM-0 T
ELECOM
B
US
I
NTERFACE
(
FOR
C
HANNEL
0)
WHEN
CONFIGURED
TO
OPERATE
IN
THE
STS-3/STM-1 M
ODE
......................................... 116
T
ABLE
20: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STS-1/STM-0 T
ELECOM
B
US
I
NTERFACE
(
WHEN
CONFIGURED
TO
OPERATE
IN
THE
STS-
3/STM-1 M
ODE
) ......................................................................................................................................................... 116
1.4.4 THE TRANSMIT STS-1/STM-0 TELECOM BUS INTERFACE TIMING..................................................................... 116
F
IGURE
20. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
T
RANSMIT
STS-1/STM-0 T
ELECOM
B
US
I
N
-
TERFACE
..................................................................................................................................................................... 117
T
ABLE
21: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STS-1/STM-0 T
ELECOM
B
US
I
NTERFACE
..................................................... 117
1.4.5 THE TRANSMIT STS-1/STM-0 TELECOM BUS INTERFACE TIMING (FOR CHANNEL 0 WHEN CONFIGURED TO OP-
ERATE IN THE STS-3/STM-1 MODE)......................................................................................................................... 117
F
IGURE
21. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
T
RANSMIT
STS-1/STM-0 T
ELECOM
B
US
I
N
-
TERFACE
ASSOCIATED
WITH
C
HANNEL
0 (
WHEN
CONFIGURED
TO
OPERATE
IN
THE
STS-3/STM-1 M
ODE
)....................... 118
T
ABLE
22: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STS-1/STM-0 T
ELECOM
B
US
I
NTERFACE
,
FOR
C
HANNEL
0
WHEN
IT
HAS
BEEN
CON
-
FIGURED
TO
OPERATE
IN
THE
STS-3/STM-1 M
ODE
...................................................................................................... 118
1.5 TRANSMIT TOH OVERHEAD INPUT PORT.................................................................................................. 118
F
IGURE
22. I
LLUSTRATION
OF
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
TOH O
VERHEAD
I
NPUT
P
ORT
.............................................. 119
T
ABLE
23: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
TOH O
VERHEAD
I
NPUT
P
ORT
....................................................................... 119
1.6 TRANSMIT POH OVERHEAD INPUT PORT.................................................................................................. 119
F
IGURE
23. I
LLUSTRATION
OF
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
POH O
VERHEAD
I
NPUT
P
ORT
.............................................. 120
T
ABLE
24: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
POH O
VERHEAD
I
NPUT
P
ORT
....................................................................... 120
1.7 TRANSMIT ORDERWIRE (E1, F1, E2) BYTE OVERHEAD INPUT PORT .................................................... 120
F
IGURE
24. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
O
RDER
-W
IRE
B
YTE
O
VERHEAD
I
NPUT
P
ORT
................. 121
T
ABLE
25: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
O
RDER
-W
IRE
B
YTE
O
VERHEAD
I
NPUT
P
ORT
................................................. 121
1.8 TRANSMIT SECTION DCC INSERTION INPUT PORT.................................................................................. 121
F
IGURE
25. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
S
ECTION
DCC O
VERHEAD
I
NSERTION
P
ORT
.................. 122
T
ABLE
26: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
O
RDER
-W
IRE
B
YTE
O
VERHEAD
I
NPUT
P
ORT
................................................. 122
1.9 TRANSMIT LINE DCC INSERTION INPUT PORT.......................................................................................... 122
F
IGURE
26. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
L
INE
DCC I
NSERTION
I
NPUT
P
ORT
................................ 123
T
ABLE
27: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
L
INE
DCC I
NSERTION
I
NPUT
P
ORT
................................................................ 123
1.10 RECEIVE TOH OVERHEAD OUTPUT PORT............................................................................................... 123
F
IGURE
27. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
R
ECEIVE
TOH O
VERHEAD
O
UTPUT
P
ORT
.................................... 124
T
ABLE
28: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
TOH O
VERHEAD
O
UTPUT
P
ORT
..................................................................... 124
1.11 RECEIVE POH OVERHEAD OUTPUT PORT............................................................................................... 124
F
IGURE
28. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
R
ECEIVE
POH O
VERHEAD
O
UTPUT
P
ORT
..................................... 125
T
ABLE
29: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
POH O
VERHEAD
O
UTPUT
P
ORT
.................................................................... 125
1.12 RECEIVE ORDERWIRE (E1, F1, E2) BYTES OVERHEAD OUTPUT PORT............................................... 125
F
IGURE
29. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
R
ECEIVE
O
RDER
-W
IRE
B
YTE
O
VERHEAD
O
UTPUT
P
ORT
................ 126
T
ABLE
30: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
O
RDER
-W
IRE
B
YTE
O
VERHEAD
O
UTPUT
P
ORT
............................................... 126
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PDF描述
XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
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