參數(shù)資料
型號: XRT94L31_07
廠商: Exar Corporation
英文描述: 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
中文描述: 3通道DS3/E3/STS-1給STS-3/STM-1映射器集成電路
文件頁數(shù): 110/133頁
文件大?。?/td> 1014K
代理商: XRT94L31_07
XRT94L31
110
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
N
OTE
:
Table 10
presents information on the Timing parameters for the Receive STS-3/STM-1 PECL Interface
These timing requirements apply to both the Primary and the Redundant Receive STS-3/STM-1 PECL
Interface blocks.
1.3.3
DS3/E3/STS-1 LIU INTERFACE TIMING INFORMATION
1.3.3.1
Ingress DS3/E3/STS-1 Interface Timing
The user should be aware of the following things about the Ingress DS3/E3/STS-1 Interface Timing.
1.
If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
configured to sample the DS3/E3/STS_1_DATA_IN and the DS3/E3/STS_1_NEG_IN input pins upon
either the rising or falling edge of DS3/E3/STS_1_CLOCK.
If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Receive STS-1 TOH
Processor block will be operating in the Single-Rail Mode (e.g., the Receive STS-1 TOH Processor block
will ONLY sample the DS3/E3/STS_1_DATA_IN input signal. It will not sample the DS3/E3/
STS_1_NEG_IN input signal.
Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Receive STS-1
TOH Processor block can be configured to sample the DS3/E3/STS_1_DATA_IN input signal, upon
either the
rising or falling edge
of DS3/E3/STS_1_CLOCK_IN.
2.
3.
F
IGURE
15. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
R
ECEIVE
STS-3/
STM-1 PECL I
NTERFACE
T
ABLE
10: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STS-3/STM-1 PECL I
NTERFACE
S
YMBOL
D
ESCRIPTION
M
IN
.
T
YP
.
M
AX
.
t6
RxL_DATA to rising edge of RxL_CLKL set-up time requirements
200ps
t7
Rising edge of RxL_CLKL to RxL_DATA hold time requirements
200ps
RxL_CLKL_p
RxL_CLKL_n
RxL_Data_n
RxL_Data_p
t6
t7
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XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
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