參數(shù)資料
型號(hào)： XRT94L31_07
廠商： Exar Corporation
英文描述： 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
中文描述： 3通道DS3/E3/STS-1給STS-3/STM-1映射器集成電路
文件頁(yè)數(shù)： 130/133頁(yè)
文件大小： 1014K
代理商： XRT94L31_07
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XRT94L31
I
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS.......................................................................................................................................... 1
FEATURES................................................................................................................................................. 1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT94L31 ............................................................................................................................... 2
ORDERING INFORMATION....................................................................................................................... 2
PIN DESCRIPTION
OF
THE
XRT94L31 (R
EV
. B) ........................................................................................ 3
1.0 ELECTRICAL CHARACTERISTIC INFORMATION FOR THE XRT94L31 DEVICE ............................ 96
1.1 DC ELECTRICAL CHARACTERISTIC INFORMATION ................................................................................... 96
T
ABLE
1: DC C
HARACTERISTIC
(A
PPLIES
TO
ALL
TTL-L
EVEL
I
NPUT
AND
CMOS L
EVEL
O
UTPUT
PINS
- A
MBIENT
T
EMPERATURE
= 25°C)
96
T
ABLE
2: DC C
HARACTERISTICS
(A
PPLIES
TO
ALL
LVPECL I
NPUT
AND
O
UTPUT
PINS
) ..................................................................... 96
1.2 AC ELECTRICAL CHARACTERISTIC INFORMATION - MICROPROCESSOR INTERFACE TIMING.......... 96
1.2.1 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE........................................................ 96
F
IGURE
2. A
SYNCHRONOUS
M
ODE
1 - I
NTEL
T
YPE
P
ROGRAMMED
I/O T
IMING
(W
RITE
C
YCLE
)......................................................... 97
F
IGURE
3. A
SYNCHRONOUS
M
ODE
1 - I
NTEL
T
YPE
P
ROGRAMMED
I/O T
IMING
(R
EAD
C
YCLE
)........................................................... 97
T
ABLE
3: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
I
NTEL
A
SYNCHRONOUS
M
ODE
........................................................................................................................................................................... 98
1.2.2 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K) MODE................................... 98
F
IGURE
4. A
SYNCHRONOUS
M
ODE
2 - M
OTOROLA
(68K) P
ROGRAMMED
I/O T
IMING
(W
RITE
C
YCLE
)................................................ 98
F
IGURE
5. A
SYNCHRONOUS
M
ODE
2 - M
OTOROLA
(68K) P
ROGRAMMED
I/O T
IMING
(R
EAD
C
YCLE
)................................................. 99
T
ABLE
4: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
WHEN
CONFIGURED
TO
OPERATE
IN
THE
M
OTOROLA
(68K) A
SYN
-
CHRONOUS
M
ODE
.......................................................................................................................................................... 99
1.2.3 MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE........................................ 100
F
IGURE
6. S
YNCHRONOUS
M
ODE
3 - IBM P
OWER
PC 403 I
NTERFACE
T
IMING
(W
RITE
C
YCLE
)....................................................... 100
F
IGURE
7. S
YNCHRONOUS
M
ODE
3 - IBM P
OWER
PC 403 I
NTERFACE
T
IMING
(W
RITE
C
YCLE
)....................................................... 101
T
ABLE
5: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
IBM P
OWER
PC403 M
ODE
102
1.2.4 MICROPROCESSOR INTERFACE TIMING - IDT3051/52 MODE............................................................................. 103
F
IGURE
8. S
YCHRONOUS
M
ODE
4 - IDT3051/52 I
NTERFACE
T
IMING
(W
RITE
C
YCLE
)..................................................................... 103
F
IGURE
9. S
YCHRONOUS
M
ODE
4 - IDT3051/52 I
NTERFACE
T
IMING
(R
EAD
C
YCLE
)...................................................................... 104
T
ABLE
6: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
IBM P
OWER
PC403 M
ODE
104
1.2.5 MICROPROCESSOR INTERFACE TIMING - MPC860 MODE.................................................................................. 105
F
IGURE
10. MPC860 M
ODE
- T
IMING
(W
RITE
C
YCLE
).................................................................................................................. 105
F
IGURE
11. MPC860 M
ODE
- T
IMING
(R
EAD
C
YCLE
).................................................................................................................... 106
T
ABLE
7: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
MPC860 M
ODE
. 106
1.3 STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION........................................................... 107
1.3.1 STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION ...................................................................... 107
1.3.1.1 T
HE
T
RANSMIT
STS-3/STM-1 T
ELECOM
B
US
I
NTERFACE
T
IMING
........................................................................ 107
F
IGURE
12. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
T
RANSMIT
STS-3/STM-1 T
ELECOM
B
US
I
NTERFACE
.................................................................................................................................................................. 107
F
IGURE
13. A
N
I
LLUSTRATION
OF
THE
TIMING
RELATIONSHIPS
BETWEEN
THE
T
X
SBFP
INPUT
PIN
AND
THE
T
X
A_CLK
OUTPUT
PIN
WITHIN
THE
T
RANSMIT
STS-3/STM-1 T
ELECOM
B
US
I
NTERFACE
.................................................................................................... 108
T
ABLE
8: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STS-3/STM-1 T
ELECOM
B
US
I
NTERFACE
....................................................... 108
1.3.1.2 T
HE
R
ECEIVE
STS-3/STM-1 T
ELECOM
B
US
I
NTERFACE
T
IMING
.......................................................................... 108
F
IGURE
14. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
R
ECEIVE
STS-3/STM-1 T
ELECOM
B
US
I
N
-
TERFACE
..................................................................................................................................................................... 109
T
ABLE
9: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STS-3/STM-1 T
ELECOM
B
US
I
NTERFACE
........................................................ 109
1.3.2 STS-3/STM-1 PECL INTERFACE TIMING INFORMATION....................................................................................... 109
1.3.2.1 T
HE
R
ECEIVE
STS-3/STM-1 PECL I
NTERFACE
T
IMING
....................................................................................... 109
F
IGURE
15. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
R
ECEIVE
STS-3/STM-1 PECL I
NTERFACE
110
T
ABLE
10: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STS-3/STM-1 PECL I
NTERFACE
.................................................................... 110
1.3.3 DS3/E3/STS-1 LIU INTERFACE TIMING INFORMATION......................................................................................... 110
1.3.3.1 I
NGRESS
DS3/E3/STS-1 I
NTERFACE
T
IMING
....................................................................................................... 110
F
IGURE
16. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
DS3/E3/STS-1
SIGNALS
THAT
ARE
INPUT
TO
THE
DS3/E3/STS-1 LIU I
NTER
-
FACE
(
IN
THE
I
NGRESS
D
IRECTION
) .............................................................................................................................. 111
1.3.4 INGRESS TIMING FOR DS3/E3 APPLICATIONS ..................................................................................................... 111
T
ABLE
11: T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
DS3/E3 A
PPLICATIONS
(
RISING
EDGE
OF
DS3/E3/
STS_1_CLOCK_IN) .................................................................................................................................................. 111
T
ABLE
12: T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
DS3/E3 A
PPLICATIONS
(
FALLING
EDGE
OF
DS3/E3/
STS_1_CLOCK_IN) .................................................................................................................................................. 111
相關(guān)PDF資料
PDF描述
XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
XRT94L31IB 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
XRT94L43A SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
XRT94L43 SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER
XRT94L43IB SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER
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參數(shù)描述
XRT94L31ES-L04 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT94L31IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT94L31IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT94L31IB-L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Mapper / Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT94L33 制造商:EXAR 制造商全稱:EXAR 功能描述:-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SONET REGISTERS
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