參數(shù)資料
型號： XRT86VL34_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 41/63頁
文件大小： 402K
代理商： XRT86VL34_1
XRT86VL34
38
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ACK0
ACK1
T2
U2
I
-
DMA Cycle Acknowledge Input—DMA Controller 0 (Write):
The external DMA Controller will assert this input pin “Low”
when the following two conditions are met:
1.
After the DMA Controller, within the Framer has asserted
(toggled “Low”), the Req_0 output signal.
2.
When the external DMA Controller is ready to transfer
data from external memory to the selected Transmit
HDLC buffer.
At this point, the DMA transfer between the external memory
and the selected Transmit HDLC buffer may begin.
After completion of the DMA cycle, the external DMA Controller
will negate this input pin after the DMA Controller within the
Framer has negated the Req_0 output pin. The external DMA
Controller must do this in order to acknowledge the end of the
DMA cycle.
DMA Cycle Acknowledge Input—DMA Controller 1 (Read):
The external DMA Controller asserts this input pin “Low” when
the following two conditions are met:
1.
After the DMA Controller, within the Framer has asserted
(toggled "Low"), the Req_1 output signal.
2.
When the external DMA Controller is ready to transfer
data from the selected Receive HDLC buffer to external
memory.
At this point, the DMA transfer between the selected Receive
HDLC buffer and the external memory may begin.
After completion of the DMA cycle, the external DMA Controller
will negate this input pin after the DMA Controller within the
Framer has negated the Req_1 output pin. The external DMA
Controller will do this in order to acknowledge the end of the
DMA cycle.
N
OTE
:
This pin is internally pulled “High” with a 50k
Ω
resistor.
BLAST
U10
I
-
Last Cycle of Burst Indicator Input:
If the Microprocessor Interface is operating in the Intel-I960
Mode, then this input pin is used to indicate (to the Micropro-
cessor Interface block) that the current data transfer is the last
data transfer within the current burst operation.
The Microprocessor should assert this input pin (by toggling it
“Low”) in order to denote that the current READ or WRITE
operation (within a BURST operation) is the last operation of
this BURST operation.
N
OTES
:
1.
If the user has configured the Microprocessor
Interface to operate in the Intel-Asynchronous, the
Motorola-Asynchronous or the Power PC 403 Mode,
then he/she should tie this input pin to GND.
2.
This pin is internally pulled “High” with a 50k
Ω
resistor.
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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相關代理商/技術參數(shù)
參數(shù)描述
XRT86VL34ES 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB 功能描述:網(wǎng)絡控制器與處理器 IC 4 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB-F 功能描述:網(wǎng)絡控制器與處理器 IC 4-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
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