參數(shù)資料
型號(hào): XRT86VL34_1
廠商: Exar Corporation
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 34/63頁(yè)
文件大?。?/td> 402K
代理商: XRT86VL34_1
XRT86VL34
31
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
T4
U3
V8
V9
T10
V10
U11
R11
I/O
8
Bidirectional Microprocessor Data Bus
These pins are used to drive and receive data over the bi-direc-
tional data bus, whenever the Microprocessor performs READ
or WRITE operations with the Microprocessor Interface of the
XRT86VL34 device.
When DMA interface is enabled, these 8-bit bidirectional data
bus is also used by the T1/E1 Framer or the external DMA
Controller for storing and retrieving information.
REQ0
R1
O
8
DMA Cycle Request Output—DMA Controller 0 (Write)
:
These output pins are used to indicate that DMA transfers
(Write) are requested by the T1/E1 Framer.
On the transmit side (i.e., To transmit data from external DMA
controller to HDLC buffers within the XRT86VL34), DMA trans-
fers are only requested when the transmit buffer status bits
indicate that there is space for a complete message or cell.
The DMA Write cycle starts by T1/E1 Framer asserting the
DMA Request (REQ0) ‘low’, then the external DMA controller
should drive the DMA Acknowledge (ACK0) ‘low’ to indicate
that it is ready to start the transfer. The external DMA controller
should place new data on the Microprocessor data bus each
time the Write Signal is Strobed low if the WR is configured as
a Write Strobe. If WR is configured as a direction signal, then
the external DMA controller would place new data on the
Microprocessor data bus each time the Read Signal (RD) is
Strobed low.
The Framer asserts this output pin (toggles it "Low") when at
least one of the Transmit HDLC buffers are empty and can
receive one more HDLC message.
The Framer negates this output pin (toggles it “High”) when the
HDLC buffer can no longer receive another HDLC message.
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