參數(shù)資料
型號: XRT86VL34_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 14/63頁
文件大?。?/td> 402K
代理商: XRT86VL34_1
XRT86VL34
11
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
TxCHCLK0
TxCHCLK1
TxCHCLK2
TxCHCLK3
A13
C15
N17
V17
O
8
Transmit Channel Clock Output Signal (TxCHCLKn):
The exact function of this pin depends on whether or not the transmit
framer enables the transmit fractional/signaling interface to input frac-
tional data, as described below.
If transmit fractional/signaling interface is disabled:
This pin indicates the boundary of each time slot of an outbound DS1/
E1 frame. In T1 mode, each of these output pins is a 192kHz clock
which pulses "High" during the LSB of each 24 time slots. In E1 mode,
each of these output pins is a 256kHz clock which pulses "High" dur-
ing the LSB of each 32 time slots. The Terminal Equipment can use
this clock signal to sample the TxCHN0 through TxCHN4 time slot
identifier pins to determine which time slot is being processed.
If transmit fractional/signaling interface is enabled:
TxCHCLKn is the fractional interface clock which either outputs a
clock signal for the time slot that has been configured to input frac-
tional data, or outputs an enable signal for the fractional time slot so
that fractional data can be clocked into the device using the TxSER-
CLK pin.
N
OTE
:
Transmit fractional interface can be enabled by programming
to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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