參數(shù)資料
型號(hào)： XRT86VL34_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 16/63頁(yè)
文件大小： 402K
代理商： XRT86VL34_1
XRT86VL34
13
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
TxCHN0_1/
TxFrTD0
TxCHN1_1/
TxFrTD1
TxCHN2_1/
TxFrTD2
TxCHN3_1/
TxFrTD3
D12
F17
M17
U13
I/O
8
Transmit Time Slot Octet Identifier Output 1 (TxCHNn_1) / Trans-
mit Serial Fractional Input (TxFrTDn):
The exact function of these pins depends on whether or not the trans-
mit framer enables the transmit fractional/signaling interface, as
described below:
If transmit fractional/signaling interface is disabled - TxCHNn_1
These output signals (TxCHNn_4 through TxCHNn_0) reflect the five-
bit binary value of the current time slot being processed by the trans-
mit serial interface. Terminal Equipment can use the TxCHCLK to
sample the five output pins of each channel in order to identify the
time slot being processed. This pin indicates Bit 1 of the time slot
channel being processed.
If transmit fractional/signaling interface is enabled - TxFrTDn
These pins are used as the fractional data input pins to input frac-
tional DS1/E1 payload data which will be inserted within an outbound
DS1/E1 frame. In this mode, terminal equipment can use either
TxCHCLK or TxSERCLK to clock in fractional DS1/E1 payload data
depending on the framer configuration.
N
OTES
:
1.
Transmit fractional/Signaling interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from register
0xn120 to ‘1’.
2.
These 8 pins are internally pulled “Low” for each channel.
TxCHN0_2/
Tx32MHz0
TxCHN1_2/
Tx32MHz1
TxCHN2_2/
Tx32MHz2
TxCHN3_2/
Tx32MHz3
B13
G17
T16
T12
O
8
Transmit Time Slot Octet Identifier Output 2 (TxCHNn_2) / Trans-
mit 32.678MHz Clock Output (Tx32MHZ):
The exact function of these pins depends on whether or not the trans-
mit framer enables the transmit fractional/signaling interface, as
described below:
If transmit fractional/signaling interface is disabled - TxCHNn_2
These output signals (TxCHNn_4 through TxCHNn_0) reflect the five-
bit binary value of the current time slot being processed by the trans-
mit serial interface. Terminal Equipment can use the TxCHCLK to
sample the five output pins of each channel in order to identify the
time slot being processed. This pin indicates Bit 2 of the time slot
channel being processed.
If transmit fractional/signaling interface is enabled - Tx32MHz
These pins are used to output a 32.678MHz clock reference which is
derived from the MCLKIN input pin.
N
OTE
:
Transmit fractional interface can be enabled by programming
to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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