TABLE
參數(shù)資料
型號： XRT86VL32IB-F
廠商： Exar Corporation
文件頁數(shù)： 96/155頁
文件大小： 0K
描述： IC LIU/FRAMER T1/E1/J1 2CH 225BG
標(biāo)準(zhǔn)包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL32
40
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 27: GAPPED CLOCK CONTROL REGISTER (GCCR)
HEX ADDRESS: 0Xn11E
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
FrOutclk
R/W
0
Framer Output Clock Reference
This bit is used to enable or disable high-speed T1 rate on the
T1OSCCLK and the E1OSCCLK output pins.
By default, the output clock reference on T1OSCCLK and
E1OSCCLK output pins are set to 1.544MHz/2.048MHz respectively.
By setting this bit to a “1”, the output clock reference on the
T1OSCLK and the E1OSCCLK are changed to 49.408MHz/
65.536MHz respectively.
0 = Disables high-speed rate to be output on the T1OSCCLK and
E1OSCCLK output pins.
1 = Enables high-speed rate to be output on the T1OSCCLK and
E1OSCCLK output pins.
[6:2] Reserved
-
Reserved
1
TxGCCR
R/W
0
Transmit Gapped Clock Interface
This bit is used to enable or disable the transmit gapped clock inter-
face operating at 2.048Mbit/s in DS-1 mode. In this application, 63
gaps (missing data) are inserted so that the overall bit rate is reduced
to 1.544Mbit/s.
If the transmit Gapped Clock Interface is enabled:
TxMSYNC is used as the 2.048MHz Gapped Clock Input.
TxSER is used as the 2.048MHz Gapped Data Input.
TxSERCLK must be a 1.544MHz clock input.
0 = Disables the transmit gapped clock interface.
1 = Enables the transmit gapped clock interface.
0
RxGCCR
R/W
0
Receive Gapped Clock Interface
This bit is used to enable or disable the receive gapped clock inter-
face operating at 2.048Mbit/s in DS-1 mode. In this application, 63
gaps (missing data) are extracted so that the overall bit rate is
reduced to 1.544Mbit/s.
If the Receive Gapped Clock Interface is enabled:
RxSERCLK should be configured as a Gapped clock input at
2.048MHz so that a 2.048MHz Gapped Clock can be applied to the
Framer block.
RxSER is used as the 2.048MHz Gapped Data Output. The position
of the gaps will be determined by the gaps placed on RxSERCLK by
the user.
0 = Disables the Receive Gapped Clock Interface
1 = Enables the Receive Gapped Clock Interface
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