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XRT86VL32
70
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
NOTE: The default value for register address 0xn340 = 0x01, 0xn341-0xn34F = 0xD0, 0xn350 = 0xB3, 0xn351-0xn35F =
0xD0
1
TxSIGSRC[1]
R/W
See Note
Channel signaling control
These bits determine the source for signaling information, see table
below.
0
TxSIGSRC[0]
R/W
See Note
TABLE 52: TRANSMIT SIGNALING CONTROL REGISTER 0-23 (TSCR 0-23)
HEX ADDRESS: 0Xn340 TO 0XN357
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
TXSIGSRC[1:0]
SIGNALING SOURCE SELECTED
00/11
Signaling data is inserted from input PCM
data (TxSERn pin)
01
Signaling data is inserted from this register
(TSCRs).
10
Signaling data is inserted from the Transmit
Signaling input pin (TxSIG_n) if the Transmit
Signaling Interface bit is enabled (i.e.
TxFr1544 bit = 1 in the Transmit Interface
Control Register (TICR) Register 0xn120),