參數(shù)資料
型號： XRT86VL32IB-F
廠商： Exar Corporation
文件頁數(shù)： 33/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 2CH 225BG
標準包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應商設備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL32
123
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
1
RxAIS-CI
RUR/
WC
0
Change in Receive AIS-CI Condition Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change in AIS-
CI Condition” interrupt within the T1 Receive Framer Block has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block detects the AIS-CI Condition.
2. Whenever the Receive T1 Framer block clears the AIS-CI Condition
0 = Indicates the “Change in AIS-CI Condition” interrupt has NOT occurred
since the last read of this register
1 = Indicates the “Change in AIS-CI Condition” interrupt has occurred since
the last read of this register
0
RxRAI-CI
RUR/
WC
0
Change in Receive RAI-CI Condition Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change in RAI-
CI Condition” interrupt within the T1 Receive Framer Block has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block detects the RAI-CI Condition.
2. Whenever the Receive T1 Framer block clears the RAI-CI Condition
0 = Indicates the “Change in RAI-CI Condition” interrupt has NOT occurred
since the last read of this register
1 = Indicates the “Change in RAI-CI Condition” interrupt has occurred since
the last read of this register
TABLE 105: CUSTOMER INSTALLATION ALARM STATUS REGISTER (CIAIER)
HEX ADDRESS: 0XnB41
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
1
RxAIS-CI_ENB
R/W
0
Change in Receive AIS-CI Condition Interrupt Enable
This bit enables or disables the “Change in AIS-CI Condition” interrupt within
the T1 Receive Framer Block.
If this interrupt is enabled, then the Receive T1 Framer block will generate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block detects the AIS-CI Condition.
2. Whenever the Receive T1 Framer block clears the AIS-CI Condition
0 - Disables the “Change in AIS-CI Condition” interrupt.
1 - Enables the “Change in AIS-CI Condition” interrupt.
0
RxRAI-CI_ENB
R/W
0
Change in Receive RAI-CI Condition Interrupt Enable
This bit enables or disables the “Change in RAI-CI Condition” interrupt within
the T1 Receive Framer Block.
If this interrupt is enabled, then the Receive T1 Framer block will generate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block detects the RAI-CI Condition.
2. Whenever the Receive T1 Framer block clears the AIS-CI Condition
0 - Disables the “Change in RAI-CI Condition” interrupt.
1 - Enables the “Change in RAI-CI Condition” interrupt.
TABLE 104: CUSTOMER INSTALLATION ALARM STATUS REGISTER (CIASR)
HEX ADDRESS: 0XnB40
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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