TABLE
參數(shù)資料
型號： XRT86VL32IB-F
廠商： Exar Corporation
文件頁數(shù)： 144/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 2CH 225BG
標準包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL32
84
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 70: PMON LAPD1 FRAME CHECK SEQUENCE ERROR COUNTER 1 (LFCSEC1)
HEX ADDRESS: 0Xn90C
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
FCSEC1[7]
RUR
0
Performance Monitor - LAPD 1 Frame Check Sequence Error
Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Frame Check Sequence Error have been detected by
the LAPD Controller 1 since the last read of this register.
6
FCSEC1[6]
RUR
0
5
FCSEC1[5]
RUR
0
4
FCSEC1[4]
RUR
0
3
FCSEC1[3]
RUR
0
2
FCSEC1[2]
RUR
0
1
FCSEC1[1]
RUR
0
FCSEC1[0]
RUR
0
TABLE 71: PRBS BIT ERROR COUNTER MSB (PBECU)
HEX ADDRESS: 0Xn90D
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
PRBSE[15]
RUR
0
Performance Monitor - T1 PRBS Bit Error 16-Bit Counter -
Upper Byte:
These RESET-upon-READ bits, along with that within the “PMON
T1 PRBS Bit Error Counter Register LSB” combine to reflect the
cumulative number of instances that the ReceiveT1 PRBS Bit errors
has been detected by the Receive T1 Framer block since the last
read of this register.
This register contains the Most Significant byte of this 16-bit of the
Receive T1 PRBS Bit Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
PRBSE[14]
RUR
0
5
PRBSE[13]
RUR
0
4
PRBSE[12]
RUR
0
3
PRBSE[11]
RUR
0
2
PRBSE[10]
RUR
0
1
PRBSE[9]
RUR
0
PRBSE[8]
RUR
0
TABLE 72: PRBS BIT ERROR COUNTER LSB (PBECL)
HEX ADDRESS: 0Xn90E
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
PRBSE[7]
RUR
0
Performance Monitor - T1 PRBS Bit Error 16-Bit Counter -
Lower Byte:
These RESET-upon-READ bits, along with that within the “PMON
T1 PRBS Bit Error Counter Register MSB” combine to reflect the
cumulative number of instances that the ReceiveT1 PRBS Bit errors
has been detected by the Receive T1 Framer block since the last
read of this register.
This register contains the Least Significant byte of this 16-bit of the
Receive T1 PRBS Bit Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
PRBSE[6]
RUR
0
5
PRBSE[5]
RUR
0
4
PRBSE[4]
RUR
0
3
PRBSE[3]
RUR
0
2
PRBSE[2]
RUR
0
1
PRBSE[1]
RUR
0
PRBSE[0]
RUR
0
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