XRT86L30
66
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 47: RECEIVE INTERFACE CONTROL REGISTER (RICR) - E1 MODE
Register 33 - E1 Mode
RECEIVE INTERFACE CONTROL REGISTER (RICR)
0X0122
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RxSyncFrD
R/W
0
Rx synchronous fractional data interface
0 = Fractional data is clocked out from the chip using RxChCLK
1 = RxChClk is used to output fractional data enable instead of being fraction
data clock. In this mode, fractional data is clocked out of the chip using
RxSerClk (ungapped). RxChn still indicates the time slot number if RxFr2048
is not 1, RxIMODE[1:0] = 0, and RxMUXEN = 0.
6
Reserved
-
Reserved
5
RxPLClkEnb/
R/W
0
Rx Payload Clock Enable
1 = RxSerClk outputs Rx clock with OH bit period blocked while in 2.048MHz
clock
output mode.
RxSyncislow
RxSync is low
In H.100 and HMVIP Mode
1 = RxSync active low.
0 = RxSync active high.
4
RxFr2048
R/W
0
Clock Inversion
1 = RxChn[0]/RxSig outputs signaling information, RxChn[1]/RxFrTD will out-
put
fractional channel data in 2.048 MHz mode and RxChn[2] will output the
serial
channel number of each time slot.
0 = RxChn[4:0] outputs the parallel channel number as usual.
3
RxICLKINV
N/A
0
Clock Inversion
0 = Data transition happens on the rising edge of the transmit clocks.
1 = Data transition happens on the falling edge of the transmit clocks.
2
RxMUXEN
R/W
0
Mux Enable
0 = No channel Multiplexing.
1 = Four channels are multiplexed in single serial stream.