
XRT86L30
IX
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
Table 59:: Transmit Sa4 Register .................................................................................................................................... 73
Table 60:: Transmit Sa5 Register .................................................................................................................................... 74
Table 61:: Transmit Sa6 Register .................................................................................................................................... 74
Table 62:: Transmit Sa7 Register .................................................................................................................................... 74
Table 63:: Transmit Sa8 Register .................................................................................................................................... 74
Table 64:: Receive Sa4 Register ..................................................................................................................................... 75
Table 65:: Receive Sa5 Register ..................................................................................................................................... 75
Table 66:: Receive Sa6 Register ..................................................................................................................................... 75
Table 67:: Receive Sa7 Register ..................................................................................................................................... 75
Table 68:: Receive Sa8 Register ..................................................................................................................................... 76
Table 69:: Data Link Control Register .............................................................................................................................. 76
Table 70:: Transmit Data Link Byte Count Register ......................................................................................................... 77
Table 71:: Receive Data Link Byte Count Register .......................................................................................................... 78
Table 72:: Data Link Control Register .............................................................................................................................. 79
Table 73:: Transmit Data Link Byte Count Register ......................................................................................................... 80
Table 74:: Receive Data Link Byte Count Register .......................................................................................................... 81
Table 75:: Device ID Register .......................................................................................................................................... 81
Table 76:: Revision ID Register ....................................................................................................................................... 81
Table 77:: Transmit Channel Control Register 0 to 31 E1 Mode ..................................................................................... 81
Table 78:: Transmit Channel Control Register 0 to 31 T1 Mode ..................................................................................... 82
Table 79:: Transmit User Code Register 0 to 31 ............................................................................................................. 82
Table 80:: Transmit Signaling Control Register x - E1 Mode ........................................................................................... 82
Table 81:: Transmit Signaling Control Register x - T1 Mode ........................................................................................... 83
Table 82:: Receive Channel Control Register x (RCCR 0-31) - E1 Mode ....................................................................... 83
Table 83:: Receive Channel Control Register x (RCCR 0-23) - T1 Mode ....................................................................... 84
Table 84:: Receive User Code Register x (RUCR 0-31) .................................................................................................. 85
Table 85:: Receive Signaling Control Register x (RSCR) (0-31) ..................................................................................... 86
Table 86:: Receive Substitution Signaling Register (RSSR) E1 Mode ............................................................................ 86
Table 87:: Receive Substitution Signaling Register (RSSR) T1 Mode ............................................................................ 87
Table 88:: Receive Signaling Array Register 0 to 31 ....................................................................................................... 87
Table 89:: LAPD Buffer 0 Control Register ...................................................................................................................... 87
Table 91:: PMON T1/E1 Receive Line Code (bipolar) Violation Counter ........................................................................ 88
Table 92:: PMON T1/E1 Receive Line Code (bipolar) Violation Counter ........................................................................ 88
Table 90:: LAPD Buffer 1 Control Register ...................................................................................................................... 88
Table 93:: PMON T1/E1 Receive Framing Alignment Bit Error Counter ......................................................................... 89
Table 94:: PMON T1/E1 Receive Framing Alignment Bit Error Counter ......................................................................... 89
Table 95:: PMON T1/E1 Receive Severely Errored Frame Counter ............................................................................... 89
Table 96:: PMON T1/E1 Receive CRC-4 Block Error Counter - MSB ............................................................................. 90
Table 97:: PMON T1/E1 Receive CRC-4 Block Error Counter - LSB .............................................................................. 90
Table 98:: PMON T1/E1 Receive Far-End BLock Error Counter - MSB .......................................................................... 91
Table 99:: PMON T1/E1 Receive Far End Block Error Counter ...................................................................................... 91
Table 100:: PMON T1/E1 Receive Slip Counter .............................................................................................................. 91
Table 101:: PMON T1/E1 Receive Loss of Frame Counter ............................................................................................. 92
Table 102:: PMON T1/E1 Receive Change of Frame Alignment Counter ....................................................................... 92
Table 103:: PMON LAPD T1/E1 Frame Check Sequence Error Counter 1 ..................................................................... 92
Table 104:: T1/E1 PRBS Bit Error Counter MSB ............................................................................................................. 93
Table 105:: T1/E1 PRBS Bit Error Counter LSB .............................................................................................................. 93
Table 106:: T1/E1 Transmit Slip Counter ......................................................................................................................... 93
Table 107:: T1/E1 Excessive Zero Violation Counter MSB ............................................................................................. 94
Table 108:: T1/E1 Excessive Zero Violation Counter LSB .............................................................................................. 94
Table 109:: T1/E1 Frame Check Sequence Error Counter 2 ........................................................................................... 94
Table 110:: T1/E1 Frame Check Sequence Error Counter 3 ........................................................................................... 95
Table 111:: Block Interrupt Status Register ..................................................................................................................... 95
Table 112:: Block Interrupt Enable Register .................................................................................................................... 96
Table 113:: Alarm & Error Interrupt Status Register ........................................................................................................ 97
Table 114:: Alarm & Error Interrupt Enable Register - E1 Mode ...................................................................................... 98
Table 115:: Alarm & Error Interrupt Enable Register -T1 Mode ....................................................................................... 99
Table 116:: Framer Interrupt Status Register E1 Mode ................................................................................................. 100
Table 117:: Framer Interrupt Status Register T1 Mode ................................................................................................. 101
Table 118:: Framer Interrupt Enable Register E1 Mode ................................................................................................ 102