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參數(shù)資料
| 型號： | XRT83SH314IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 80/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 14CH 304TBGA |
| 標準包裝： | 27 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 14/14 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 托盤 |
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XRT83SH314
4
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.4
PIN DESCRIPTIONS (BY FUNCTION)
MICROPROCESSOR
NAME
PIN
TYPE
DESCRIPTION
CS
A22
I
Chip Select Input
Active low signal. This signal enables the microprocessor interface by pulling
chip select "Low". The microprocessor interface is disabled when the chip
select signal returns "High".
ALE_TS
C19
I
Address Latch Enable Input (Transfer Start)
See the Microprocessor section of this datasheet for a description.
WR_R/W
A20
I
Write Strobe Input (Read/Write)
See the Microprocessor section of this datasheet for a description.
RD_WE
D18
I
Read Strobe Input (Write Enable)
See the Microprocessor section of this datasheet for a description.
RDY_TA
AA3
O
Ready Output (Transfer Acknowledge)
See the Microprocessor section of this datasheet for a description.
INT
B3
O
Interrupt Output
Active low signal. This signal is asserted "Low" when a change in alarm status
occurs. Once the status registers have been read, the interrupt pin will return
"High". GIE (Global Interrupt Enable) must be set "High" in the appropriate
global register to enable interrupt generation.
NOTE: This pin is an open-drain output that requires an external 10K
pull-up
resistor.
PCLK
AB2
I
Micro Processor Clock Input
In a synchronous microprocessor interface, PCLK is used as the internal tim-
ing reference for programming the LIU.
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
A23
E20
C22
Y18
AA19
AB20
AC21
AB21
AA20
Y19
AC22
I
Address Bus Input
ADDR[10:8] is used as a chip select decoder. The LIU has 5 chip select output
pins for enabling up to 5 additional devices for accessing internal registers.
The LIU has the option to select itself (master device), up to 5 additional
devices, or all 6 devices simultaneously by setting the ADDR[10:8] pins speci-
fied below. ADDR[7:0] is a direct address bus for permitting access to the
internal registers.
ADDR[10:8]
000 = Master Device
001 = Chip Select Output 1 (Pin B21)
010 = Chip Select Output 2 (Pin D19)
011 = Chip Select Output 3 (Pin C20)
100 = Chip Select Output 4 (Pin A21)
101 = Chip Select Output 5 (Pin B20)
110 = Reserved
111 = All Chip Selects Active Including the Master Device
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SH314IB-SAK | 制造商:Exar Corporation 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 制造商:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38_0609 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38ES | 功能描述:外圍驅(qū)動器與原件 - PCI 8 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SH38IB | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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