參數(shù)資料
型號: XRT83SH314IB-F
廠商: Exar Corporation
文件頁數(shù): 24/101頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝: 27
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 托盤
XRT83SH314
25
REV. 1.0.4
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
3.0
TRANSMIT PATH LINE INTERFACE
The transmit path of the XRT83SH314 LIU consists of 14 independent T1/E1/J1 transmitters. The following
section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs.
A
simplified block diagram of the transmit path is shown in Figure 15.
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH
3.1
TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83SH314 can be programmed to sample the inputs on
either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising
edge of TCLK, set TCLKE to "1" in the appropriate global register. Figure 16 is a timing diagram of the
transmit input data sampled on the falling edge of TCLK. Figure 17 is a timing diagram of the transmit input
data sampled on the rising edge of TCLK. The timing specifications are shown in Table 6.
FIGURE 16. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
& Pattern Gen
Line Driver
TTIP
TRING
TCLK
TNEG
TPOS
TCLK
TPOS
or
TNEG
TCLK
R
TCLK
F
T
HO
T
SU
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參數(shù)描述
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