參數(shù)資料
型號: XRT83L38IB
廠商: Exar Corporation
文件頁數(shù): 42/87頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 225BGA
標準包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83L38
44
REV. 1.0.2
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
DIGITAL LOOP-BACK (DLOOP)
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in Figure 23.
DUAL LOOP-BACK
Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit
path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
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