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參數(shù)資料
型號： XRT83L38IB
廠商： Exar Corporation
文件頁數(shù)： 12/87頁
文件大小： 0K
描述： IC LIU T1/E1/J1 OCTAL 225BGA
標準包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83L38
2
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
FEATURES
Fully integrated eight channel long-haul or short-haul transceivers for E1,T1 or J1 applications
Adaptive Receive Equalizer for up to 36dB cable attenuation
Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping available for both T1 and E1 modes
Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps
Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz
Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
E1 and 0 to 3dB of cable attenuation for T1 modes
Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω (J1) applications
Internal and/or external impedance matching for 75Ω, 100Ω, 110Ω and 120Ω
Tri-State transmit output and receive input capability for redundancy applications
Provides High Impedance for Tx and Rx during power off
Transmit return loss meets or exceeds ETSI 300-166 standard
On-chip digital clock recovery circuit for high input jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable either in transmit or receive path
On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources
High receiver interference immunity
On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
Receive loss of signal (RLOS) output
FIGURE 2. BLOCK DIAGRAM OF THE XRT83L38 T1/E1/J1 LIU (HARDWARE MODE)
One of Eight Channels, CHANNEL_n - (n=0 : 7)
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
ICT
MCLKE1
MCLKT1
CLKSEL[2:0]
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
RTIP_n
RRING_n
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO_n
TTIP_n
TRING_n
TXON_n
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SELECT
NLCD ENABLE
QRSS ENABLE
HARWARE CONTROL
TEST
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
DRIVE
MONITOR
DFM
MCLKOUT
TAOS_n
LOOP1_n
LOOP0_n
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