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| 型號： | XRT83L38IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 24/87頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 OCTAL 225BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA |
| 供應(yīng)商設(shè)備封裝： | 225-BGA（19x19） |
| 包裝： | 托盤 |
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XRT83L38
27
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
JITTER ATTENUATOR
To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive
signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set “High” the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO
length will not be available in this mode. Jitter attenuator controls are available on a per channel basis in the
Host mode and on a global basis in the Hardware mode.
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)
The XRT83L38 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width of the 8-Channel LIU is shown in Table 2.
NOTE: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.
FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH
MAXIMUM GAP WIDTH
32-Bit
20 UI
64-Bit
50 UI
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
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| XRT83L38IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L38IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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| XRT83SH314ES | 功能描述:外圍驅(qū)動器與原件 - PCI 14 CHT1/E1LIU SH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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