參數(shù)資料
型號(hào)： XRT83L34IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 54/99頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
55
the XRT83L34 device). In this case, the Microprocessor should continue to hold the "Write Strobe" (WR*/
R/W*) input pin "LOW" until it detects the "RDY*/DTACK*" output pin toggling "HIGH".
8. After waiting the appropriate amount of time for the data (on the Bi-Directional Data Bus) to stabilize and
can be safely accepted by the Microprocessor Interface block circuitry (within the XRT83L34 device); the
XRT83L34 device will indicate that this data can be latched into the "target" address location by toggling
the RDY*/DTACK* output pin "LOW".
9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
can then terminate the WRITE cycle by toggling the WR*/R/W* (Write Strobe) input pin "HIGH".
NOTE: Once the user toggles the "WR*/R/W* (Write Strobe) input pin "HIGH", then the Microprocessor Interface (of the
XRT83L34 device) will latch the contents of the Bi-Directional Data Bus (D[7:0]) into the "target" address location o
of the chip.
Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals during
an Intel-Asynchronous Mode Write Operation.
OPERATING THE MICROPROCESSOR INTERFACE IN THE MOTOROLA-ASYNCHRONOUS MODE
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the
following Microprocessor Interface pins will assume the role that is described below in Table _.
FIGURE 26. ILLUSTRATION OF AN INTEL-ASYNCHRONOUS MODE WRITE OPERATION
ALE/AS
RD*/DS*
A[6:0]
CS*
D[7:0]
RDY/DTACK*
Data to be Written
Address of Target Register
WR*/R/W*
Microprocessor places “target”
Address value on A[6:0]
Address Decoding
Circuitry asserts
CS*
RDY* toggles “l(fā)ow” to indicate that
Valid data can be latched into “target”
Address location of chip
Write Operation begins
Here
RDY* toggles “high”
after Completion
Of Write Operation
Write Operation is
Terminated Here
Microprocessor Interface latches contents on
A[6:0] upon falling edge of ALE
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