QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 16 RDY" />
參數(shù)資料
型號(hào)： XRT83L34IVTR-F
廠商： Exar Corporation
文件頁數(shù)： 11/99頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
16
RDY_DTACK
RXMUTE
73
O
I
Ready or DTACK Output/Receive Muting upon LOS Command Input
pin:
The exact function of this input pin depends upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - READY or DTACK Output Pin:
The exact function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - RDY* - Ready Output:
If the Microprocessor Interface has been configured to operate in the Intel-
Asynchronous Mode, then this output pin will function as the "active-low"
READY output.
During a READ or WRITE cycle, the Microprocessor Interface block will tog-
gle this output pin to the logic low level, ONLY when it (the Microprocessor
Interface) is ready to complete or terminate the current READ or WRITE
cycle. Once the Microprocessor has determined that this input pin has tog-
gled to the logic "low" level, then it is now safe for it to move on and execute
the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "high" level, then the Microprocessor is
expected to extend this READ or WRITE cycle, until it detects this output pin
being toggled to the logic low level.
Motorola-Asynchronous Mode - DTACK* - Data Transfer Acknowledge
Output:
If the Microprocessor interface has been configured to operate in the Motor-
ola-Asynchronous Mode, then this output pin will function as the "active-low"
DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface block will tog-
gle this output pin to the logic low level, ONLY when it (the Microprocessor
Interface) is ready to complete or terminate the current READ or WRITE
cycle. Once the Microprocessor Interface has determined that this input pin
has toggled to the logic "low" level, then it is now safe for it to move on and
execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "HIGH" level, then the MIcroprocessor is
expected to extend this READ or WRITE cycle, until it detects this output pin
being toggled to the logic "LOW" level.
Receive Muting - Hardware mode
NOTE: Internally pulled “Low” with a 50k
resistor.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
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