QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 78
參數(shù)資料
型號(hào)： XRT83L34IV
廠商： Exar Corporation
文件頁(yè)數(shù)： 80/99頁(yè)
文件大小： 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤(pán)
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
78
TABLE 34: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION
REGISTER ADDRESS
0001110
0011110
0101110
0111110
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6-D0
B6S7_n -
B0S7_n
Arbitrary Transmit Pulse Shape, Segment 7
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the seventh time segment.
B6S7_n-B0S7_n is in signed magnitude format with B6S7_n
as the sign bit and B0S7_n as the least significant bit (LSB).
R/W
0
TABLE 35: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION
REGISTER ADDRESS
0001111
0011111
0101111
0111111
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6-D0
B6S8_n -
B0S8_n
Arbitrary Transmit Pulse Shape, Segment 8
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the eighth time segment. B6S8_n-
B0S8_n is in signed magnitude format with B6S8_n as the
sign bit and B0S8_n as the least significant bit (LSB).
R/W
0
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