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參數(shù)資料
型號(hào)： XRT83L34IV
廠商： Exar Corporation
文件頁數(shù)： 12/99頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
2
FEATURES
Fully integrated four channel long-haul or short-haul transceivers for E1,T1 or J1 applications
Adaptive Receive Equalizer for up to 36dB cable attenuation
Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping that can be used for both T1 and E1 modes.
Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps
Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz
Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
E1 and 0 to 3dB of cable attenuation for T1 modes
Supports 75 and 120 (E1), 100 (T1) and 110 (J1) applications
Internal and/or external impedance matching for 75, 100, 110 and 120
Tri-State transmit output and receive input capability for redundancy applications
Provides High Impedance for Tx and Rx during power off
Transmit return loss meets or exceeds ETSI 300-166 standard
On-chip digital clock recovery circuit for high input jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable either in transmit or receive path
On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources
High receiver interference immunity
On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
Receive loss of signal (RLOS) output
On-chip HDB3/B8ZS/AMI encoder/decoder functions
QRSS pattern generator and detection for testing and monitoring
FIGURE 2. BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HARDWARE MODE)
One of four Channels, CHANNEL_n - (n=0 : 3)
HW /HO ST
GAUG E
JASEL1
JASEL0
RXT SEL
TXTSEL
T ERSEL1
T ERSEL0
RXRES1
RXRES0
ICT
MCLK E1
MCLK T1
CLK SEL[2:0]
TPOS _n/TDATA _n
TNEG_n/CODES _n
TCLK _n
RCLK _n
RNEG_n/LCV _n
RPOS_n/RDATA _n
RLOS _n
RTIP_n
RRING_n
MAST ER CLO CK SYNT HESIZER
QRSS
PAT T ERN
GENERAT O R
DMO _n
TT IP_n
TRING _n
TXO N_n
HDB3/
B8ZS
ENCO DER
TX/RX JITTER
AT T ENUAT O R
TIMING
CONT ROL
T X FILT ER
& PULSE
SHAPER
LINE
DRIVER
LO CAL
ANALO G
LO O PBACK
REMO T E
LO O PBACK
DIGIT AL
LO O PBACK
HDB3/
B8ZS
DECO DER
TX/RX JITTER
AT T ENUAT O R
TIMING &
DAT A
RECOVERY
PEAK
DET ECT OR
& SLICER
QRSS
DET ECT OR
NET W O RK
LO O P
DET ECT OR
RX
EQ UALIZER
CONT ROL
AIS
DET ECT OR
LO S
DET ECT O R
LBO [3:0]
LOOPBACK
ENABLE
JA
SELEC
T
NLCD ENABLE
Q RSS ENABLE
HARW ARE CONT ROL
T EST
RESET
TRAT IO
SR/DR
EQ C[4:0]
TCLKE
RCLKE
RXMUTE
AT AO S
DRIVE
MO NIT O R
DFM
MCLKO UT
TAO S_n
LO O P1_n
LO O P0_n
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