QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 36 TRA" />
參數(shù)資料
型號： XRT83L34IV
廠商： Exar Corporation
文件頁數(shù)： 33/99頁
文件大小： 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
36
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 3)
INTERNAL RECEIVE TERMINATION MODE
In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83L34 is set for external termination mode at power up or at Hardware reset.
In Host mode, bit 7 in the appropriate channel register, (Table 21, “Microprocessor Register #1, Bit
Description,” on page 64), is set “High” to select the internal termination mode for that specific receive channel.
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7.
NOTE: In Hardware mode, pins RXRES[1:0] control all channels.
TABLE 6: RECEIVE TERMINATION CONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE
T1
TTIP
TRING
5
8
1:2
75 , 100
110 or 120
4
1
0.68 F
R
int
R
int
TTIP
TRING
TX
Line Driver
T2
RTIP
RRING
1
4
1:1
8
5
RTIP
RRING
RX
Equalizer
R
int
Channel _n
TPO S
TNEG
TCLK
RPO S
RNEG
RCLK
75 , 100
110 or 120
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