參數(shù)資料
型號(hào): XRT81L27IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: TQFP-128
文件頁(yè)數(shù): 25/30頁(yè)
文件大?。?/td> 194K
代理商: XRT81L27IV
á
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
23
3.0
The Receive Sections of the XRT81L27 consists of
the following blocks:
The Receive Equalizer block
The Peak Detector and Slicer block
The LOS Detector block
The Receive Output Interface block
3.1
I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
TO
THE
L
INE
The design of each channel (within the XRT81L27)
permits the user to transformer-couple or capacitive-
THE RECEIVE SECTION
couple the Receive Section to the line. Additionally,
as mentioned earlier, the specification documents for
E1 specify 75
termination loads, when transmitting
over coaxial cable, and 120
loads, when transmit-
ting over twisted-pair. Figure 13, Figure 14 and
Figure 15 present the various methods that can be
employ to interface the Receivers (of the XRT81L27)
to the line. The receive circuits of Figure 13,
Figure 14 and Figure 15 differ in the impedance at the
inputs and the line connections.
F
IGURE
12. I
LLUSTRATION
OF
HOW
TO
INTERFACE
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT81L27
TO
THE
L
INE
(
FOR
75
OR
120
A
PPLICATIONS
)
TPOS_n
TNEG_n
TClk_n
XRT81L27
TTIP_n
TRING_n
9.1
9.1
1:2
Line
Input
75
Coax
120
Twisted
Pair
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