參數(shù)資料
型號: XRT81L27IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: TQFP-128
文件頁數(shù): 18/30頁
文件大?。?/td> 194K
代理商: XRT81L27IV
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
á
16
1.2
A listing of these Command Registers, their binary/
hex Addresses and their Bit-Formats are in Table 9.
All bits are reset to zero by activation of the Reset sig-
nal (RST, pin 3). All other registers (0111 through
Description of the Command Registers
1111) (0x07 through 0x0F) in the address range are
reserved.
T
ABLE
9: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
AND
C
ONTROL
R
EGISTER
A
DDRESS
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
G
LOBAL
C
OMMAND
C
ONTROL
R
EGISTER
(R
EAD
/W
RITE
)
0000/0x00
reserved
ARAOS
EXLOS
MUTE
SR/DR
CODE
RClkP
TClkP
C
HANNEL
C
ONTROL
R
EGISTERS
(R
EAD
/W
RITE
)
0001/0x01
reserved
LLB6
LLB5
LLB4
LLB3
LLB2
LLB1
LLB0
0010/0x02
reserved
RLB6
RLB5
RLB4
RLB3
RLB2
RLB1
RLB0
0011/0x03
reserved
ALB6
ALB5
ALB4
ALB3
ALB2
ALB1
ALB0
0100/0x04
reserved
TAOS6
TAOS5
TAOS4
TAOS3
TAOS2
TAOS1
TAOS0
0101/0x05
reserved
RAOS6
RAOS5
RAOS4
RAOS3
RAOS2
RAOS1
RAOS0
0110/0x06
reserved
PDTx6
PDTx5
PDTx4
PDTx3
PDTx2
PDTx1
PDTx0
T
ABLE
10: C
OMMAND
C
ONTROL
R
EGISTER
- A
DDRESS
0000 - HEX 0
X
00
(COMMON TO ALL SEVEN CHANNELS)
B
IT
#
N
AME
F
UNCTION
R
EGISTER
TYPE
6
ARAOS
Automatic Receive All Ones:
Writing a "1" to this bit globally enables receive “all one data” insertion at
RPOS/RNEG upon receive LOS condition.
R/W
5
EXLOS
Extended LOS:
Writing a "1" to this bit extends the number of zeros at the receive input to
4096 bits before LOS is declared.
R/W
4
MUTE
Receive Output Muting:
Writing a "1" to this bit mutes the receive data output at RPOS/RNEG to a
“Low” state upon LOS detection EXCEPT when AROAS is set.
R/W
3
SR/DR
Single-rail/Dual-rail:
Writing a "1" to this bit selects
single-rail
mode operation.
Writing a "0" to select
dual-rail
mode operation.
R/W
2
CODE
Coding and Decoding:
In
Single-Rail mode
ONLY, selects HDB3 encoding and decoding when set.
Under all other conditions, AMI encoding and decoding is selected.
R/W
1
RClkP
Receive Clock Polarity:
Writing a "1" to this bit selects, receive output data to be updated on the rising
edge of RCLK and a "0" to update on the falling edge of RClk.
R/W
0
TClkP
Transmit Clock Polarity:
Writing a "1" to this bit selects, input data to be sampled on the rising edge of
TClk and a "0" to sample on the falling edge of TClk.
R/W
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