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參數(shù)資料
| 型號： | XRT81L27IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 194K |
| 代理商： | XRT81L27IV |
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
19
priority. This priority allows fast switching of channels
using “external hardware”. However, if software con-
trol is to be used, the PDTx pin must be tied low as
there is an internal pull-up resistor.
2.0
The Transmit section of the XRT81L27 consists of the
following blocks:
T
HE
T
RANSMIT
L
OGIC
B
LOCK
The Encoder block
The MUX block
THE TRANSMIT SECTION
The Timing Control block
The TX Pulse Shaper block
The Line Driver block
2.1
T
HE
T
RANSMIT
L
OGIC
B
LOCK
.
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single-Rail TTL/CMOS level data
and timing information from the Terminal Equipment.
Figure 7 illustrates the typical interface for the trans-
mission of data between the Terminal Equipment and
the Transmit Section of the XRT81L27.
2.1.1
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 8. The
XRT81L27samples the data on the TPOS and TNEG
input pins on the falling edge of TCLK. If the
XRT81L27 samples a “1” on the TPOS input pin, the
Transmit Section of the device ultimately generates a
Dual-rail input mode
positive polarity pulse via the TTIP and TRING output
pins. If the XRT81L27 samples a “1” on the TNEG in-
put pin, the Transmit Section of the device generates
a negative polarity pulse via the TTIP and TRING out-
put pins. HDB3 Encoding will already have been done
on this data.
2.1.2
Used if data is to be transmitted from the Terminal
Equipment to the XRT81L27 in Single-Rail format (a
Single-rail input mode
binary data stream) without having to convert it into a
Dual-Rail format. The Transmit Logic Block accepts
Single-Rail data via the TPOS input pin. The TClk sig-
F
IGURE
7. T
HE
I
NTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
F
ROM
THE
T
RANSMITTING
T
ERMINAL
E
QUIPMENT
TO
THE
T
RANSMIT
S
ECTION
OF
THE
XRT81L27
Equipment
(DTE)
Digital
Terminal
Equipment
TxPOS
TxNEG
TxClk
Block
Transmit
Logic
Block
F
IGURE
8. D
UAL
R
AIL
D
ATA
FROM
THE
T
ERMINAL
TCLK
TPOS
TNEG
Data 1 1 0 0
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| XRT82L24IV | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT81L27IV-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XR-T8205CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telephone Ringer |
| XR-T8205P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telephone Ringer |
| XRT82D20 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
| XRT82D20_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
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