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參數(shù)資料
| 型號(hào)： | XRT75R12IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 79/90頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT75R12
77
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 39: XRT75R12 REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_n)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/DS3_n
SR/DR_n
R/W
TABLE 40: CHANNEL CONTROL REGISTER - CHANNEL n ADDRESS LOCATION = 0XM6
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 6
Reserved
5
PRBS Enable
R/W
PRBS Generator and Receiver Enable - Channel_n:
This READ/WRITE bit-field is used to enable or disable the PRBS Generator
and Receiver within a given Channel of the XRT75R12.
If the user enables the PRBS Generator and Receiver, then the following will
happen.
1. The PRBS Generator (which resides within the Transmit Section of
the Channel) will begin to generate an unframed, 2^15-1 PRBS
Pattern (for DS3 and STS-1 applications) and an unframed, 2^23-1
PRBS Pattern (for E3 applications).
2. The PRBS Receiver (which resides within the Receive Section of the
Channel) will now be enabled and will begin to search the incoming
data for the above-mentioned PRBS patterns.
0 - Disables both the PRBS Generator and PRBS Receiver within the corre-
sponding channel.
1 - Enables both the PRBS Generator and PRBS Receiver within the corre-
sponding channel.
NOTES:
1.
To check and monitor PRBS Bit Errors, DR (Dual Rail) mode will be
over-ridden and Single Rail mode forced for the duration of this
mode. This will configure the RNEG/LCV_n output pin to function
as a PRBS Error Indicator. All errors will be flagged on this pin.
The errors will also be accumulated in the 16 bit Error counter for
the channel.
2.
If the user enables the PRBS Generator and PRBS Receiver, the
Channel will ignore the data that is being accepted from the
System-side Equipment (via the TxPOS_n and TxNEG_n input
pins) and will overwrite this outbound data with the PRBS Pattern.
3.
The system must provide an accurate and stable data-rate clock to
the TxClk_n pin during this operation.
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PDF描述 |
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| XRT75VL00DIV | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT75VL00IV-F | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT79L71IB-F | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| XRT81L27IV-F | IC LIU EI 7CH 3.3V 128TQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00D | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75VL00D_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET |
| XRT75VL00D1V-F | 制造商:Exar Corporation 功能描述: |
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