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參數(shù)資料
| 型號： | XRT75R12IB-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 71/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標準包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應商設備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT75R12
70
REV. 1.0.4
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
5
Digital LOS Defect
Declared
R/O
Digital LOS Defect Declared:
This READ-ONLY bit-field indicates whether or not the Digital LOS (Loss of
Signal) detector is declaring the LOS Defect condition.
For DS3 and STS-1 applications, the Digital LOS Detector will declare the
LOS Defect condition whenever it detects an absence of pulses (within the
incoming DS3 or STS-1 data-stream) for 160 consecutive bit-periods.
Further, (again for DS3 and STS-1 applications) the Digital LOS Detector
will clear the LOS Defect condition whenever it determines that the pulse
density (within the incoming DS3 or STS-1 signal) is at least 33%.
0 - Indicates that the Digital LOS Detector is NOT declaring the LOS Defect
Condition.
1 - Indicates that the Digital LOS Detector is currently declaring the LOS
Defect condition.
NOTES:
1.
LOS Detection (within each channel of the XRT75R12) is
performed by both an Analog LOS Detector and a Digital LOS
Detector. The LOS state of a given Channel is simply a WIRED-
OR of the LOS Defect Declare states of these two detectors.
2.
The current LOS Defect Condition (for the channel) can be
determined by reading out the contents of Bit 1 (Receive LOS
Defect Declared) within this register.
4
Analog LOS Defect
Declared
R/O
Analog LOS Defect Declared:
This READ-ONLY bit-field indicates whether or not the Analog LOS (Loss of
Signal) detector is declaring the LOS Defect condition.
For DS3 and STS-1 applications, the Analog LOS Detector will declare the
LOS Defect condition whenever it determines that the amplitude of the
pulses (within the incoming DS3/STS-1 line signal) drops below a certain
Analog LOS Defect Declaration threshold level.
Conversely, (again for DS3 and STS-1 applications) the Analog LOS Detec-
tor will clear the LOS Defect condition whenever it determines that the
amplitude of the pulses (within the incoming DS3/STS-1 line signal) has
risen above a certain Analog LOS Defect Clearance threshold level.
It should be noted that, in order to prevent "chattering" within the Analog
LOS Detector output, there is some built-in hysteresis between the Analog
LOS Defect Declaration and the Analog LOS Defect Clearance threshold
levels.
0 - Indicates that the Analog LOS Detector is NOT declaring the LOS Defect
Condition.
1 - Indicates that the Analog LOS Detector is currently declaring the LOS
Defect condition.
NOTES:
1.
LOS Detection (within each channel of the XRT75R12) is
performed by both an Analog LOS Detector and a Digital LOS
Detector. The LOS state of a given Channel is simply a WIRED-
OR of the LOS Defect Declare states of these two detectors.
2.
The current LOS Defect Condition (for the channel) can be
determined by reading out the contents of Bit 1 (Receive LOS
Defect Declared) within this register.
TABLE 34: ALARM STATUS REGISTER - CHANNEL n ADDRESS LOCATION = 0XM3
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| XRT75VL00DIV | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT75VL00IV-F | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT79L71IB-F | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| XRT81L27IV-F | IC LIU EI 7CH 3.3V 128TQFP |
| XRT82D20IW-F | IC LIU E1 SGL 28SOJ |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00D | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75VL00D_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET |
| XRT75VL00D1V-F | 制造商:Exar Corporation 功能描述: |
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