TABLE
參數(shù)資料
型號： XRT75R12IB-L
廠商： Exar Corporation
文件頁數(shù)： 61/90頁
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12
61
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 24: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Channel 5
Interrupt Sta-
tus
Channel 4
Interrupt Sta-
tus
Channel 3
Interrupt Sta-
tus
Channel 2
Interrupt Sta-
tus
Channel 1
Interrupt Sta-
tus
Channel 0
Interrupt Sta-
tus
R/O
BIT
NUMBER
NAME
TYPE
DESCRIPTION
7, 6
Reserved
5
4
3
2
1
0
Channel 5 Interrupt Status
Channel 4 Interrupt Status
Channel 3 Interrupt Status
Channel 2 Interrupt Status
Channel 1 Interrupt Status
Channel 0 Interrupt Status
R/O
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT75R12 has a
pending Channel n-related interrupt that is awaiting service. The
first six channels are serviced through this location and the other
six at address 0xE1. These two registers are used by the Host to
identify the source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user's Interrupt Service routine
should be written such that the Microprocessor will now proceed
to read out the contents of the Source Level Interrupt Status Reg-
ister - Channel n (Address Locations = 0xn2) to determine the
exact source of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to
"0" until the user has read out the contents of the Source-
Level Interrupt Status Register bit, that corresponds to the
interrupt request channel.
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