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| 型號： | XRT75R12DIB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 127/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標準包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應商設備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT75R12D
89
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
A detailed discussion on how to design with and configure the LIU device such that the end-system will meet
these Intrinsic Jitter and Wander requirements.
In a SONET system, the relevant specification requirements for Intrinsic Jitter and Wander (within a DS3 signal
that is mapped into and then de-mapped from SONET) are listed below.
Telcordia GR-253-CORE Category I Intrinsic Jitter Requirements for DS3 Applications (Section 5.6), and
ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
In general, there are three (3) sources of Jitter and Wander within an asynchronously-mapped DS3 signal that
the system designer must be aware of. These sources are listed below.
Mapping/De-Mapping Jitter
Pointer Adjustments
Clock Gapping
Each of these sources of jitter/wander will be defined and discussed in considerable detail within this Section.
In order to accomplish all of this, this particular section will discuss all of the following topics in details.
How DS3 data is mapped into SONET, and how this mapping operation contributes to Jitter and Wander
within this "eventually de-mapped" DS3 signal.
How this asynchronously-mapped DS3 data is transported throughout the SONET Network, and how
occurrences on the SONET network (such as pointer adjustments) will further contributes to Jitter and
Wander within the "eventually de-mapped" DS3 signal.
A review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications
A review of the DS3 Wander requirements per ANSI T1.105.03b-1997
A review of the Intrinsic Jitter and Wander Capabilities of the LIU in a typical system application
An in-depth discussion on how to design with and configure the LIU to permit the system to the meet the
above-mentioned Intrinsic Jitter and Wander requirements
NOTE: An in-depth discussion on SDH De-Sync Applications will be presented in the next revision of this data sheet.
8.2
MAPPING/DE-MAPPING JITTER/WANDER
Mapping/De-Mapping Jitter (or Wander) is defined as that intrinsic jitter (or wander) that is induced into a DS3
signal by the "Asynchronous Mapping" process.
This section will discuss all of the following aspects of
Mapping/De-Mapping Jitter.
How DS3 data is mapped into an STS-1 SPE
How frequency offsets within either the DS3 signal (being mapped into SONET) or within the STS-1 signal
itself contributes to intrinsic jitter/wander within the DS3 signal (being transported via the SONET network).
8.2.1
HOW DS3 DATA IS MAPPED INTO SONET
Whenever a DS3 signal is asynchronously mapped into SONET, this mapping is typically accomplished by a
PTE accepting DS3 data (from some remote terminal) and then loading this data into certain bit-fields within a
given STS-1 SPE (or Synchronous Payload Envelope).
At this point, this DS3 signal has now been
asynchronously mapped into an STS-1 signal. In most applications, the SONET Network will then take this
particular STS-1 signal and will map it into "higher-speed" SONET signals (e.g., STS-3, STS-12, STS-48, etc.)
and will then transport this asynchronously mapped DS3 signal across the SONET network, in this manner. As
this "asynchronously-mapped" DS3 signal approaches its "destination" PTE, this STS-1 signal will eventually
be de-mapped from this STS-N signal. Finally, once this STS-1 signal reaches the "destination" PTE, then this
asynchronously-mapped DS3 signal will be extracted from this STS-1 signal.
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