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參數(shù)資料

型號：	XRT75R06DIB-F
廠商：	Exar Corporation
文件頁數(shù)：	88/105頁
文件大?。?/td>	0K
描述：	IC LIU E3/DS3/STS-1 6CH 217BGA
標準包裝：	126
類型：	線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)：	6/6
規(guī)程：	DS3，E3，STS-1
電源電壓：	3.135 V ~ 3.465 V
安裝類型：	表面貼裝
封裝/外殼：	217-BBGA
供應(yīng)商設(shè)備封裝：	217-BGA（23x23）
包裝：	托盤

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XRT75R06D

SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.0

viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper

IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals

(towards the DS3 facility), then it will typically do so in the following manner.

In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal".

In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.

However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the Clock-

Signal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper

IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output

via the "Data-Signal".

Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output Clock-

Signal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the

Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period.

Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal.

One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within

the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must

handle this type of jitter is presented in “Section 8.8.2, Recommendations on Pre-Processing the Gapped

Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs

of the LIU” on page 89.

8.5

A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3

applications

The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates

that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their

corresponding requirements is summarized in Table 19, below.

TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3

APPLICATIONS

SCENARIO

DESCRIPTION

SCENARIO

NUMBER

TELCORDIA GR-253-CORE

CATEGORY I INTRINSIC

JITTER REQUIREMENTS

COMMENTS

DS3 De-Mapping

Jitter

0.4UI-pp

Includes effects of De-Mapping and Clock Gapping Jit-

ter

Single Pointer

Adjustment

0.3UI-pp + Ao