If the LIU h" />
參數(shù)資料
型號(hào)： XRT75R06DIB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 100/105頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 6CH 217BGA
標(biāo)準(zhǔn)包裝： 126
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 6/6
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 217-BBGA
供應(yīng)商設(shè)備封裝： 217-BGA（23x23）
包裝： 托盤(pán)
XRT75R06D
á
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
89
If the LIU has been configured to operate in the Hardware Mode.
Then the user should tie pin 43 (JATx/JARx*) to "1".
e. Enable the "SONET APS Recovery Time" Mode
Finally, if the user intends to use the LIU in an Application that is required to reacquire proper SONET and DS3
traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-CORE), then
the user should set Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control" Register,
to "0" as depicted below.
NOTES:
1.
The ability to disable the "SONET APS Recovery Time" mode is only available if the LIU is operating in the Host
Mode. If the LIU is operating in the "Hardware" Mode, then this "SONET APS Recovery Time Mode" feature will
always be enabled.
2.
The "SONET APS Recovery Time" mode will be discussed in greater detail in “Section 8.8.3, How does the LIU
8.8.2
Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device)
prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU
In order to minimize the effects of "Clock-Gapping" Jitter within the DS3 signal that is ultimately transmitted to
the DS3 Line (or facility), we recommend that some "pre-processing" of the "Data-Signals" and "Clock-Signals"
(which are output from the Mapper device) be implemented prior to routing these signals to the "Transmit
Inputs" of the LIU.
8.8.2.1
SOME NOTES PRIOR TO STARTING THIS DISCUSSION:
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2
BIT 1BIT 0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/W
00
000
0
11
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7BIT 6BIT 5
BIT 4BIT 3BIT 2BIT 1BIT 0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/WR/W
R/W
00
0
00
001
相關(guān)PDF資料
PDF描述
XRT75R06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
XRT75R12DIB-L IC LIU E3/DS3/STS-1 12CH 420TBGA
XRT75R12IB-L IC LIU E3/DS3/STS-1 12CH 420TBGA
XRT75VL00DIV IC LIU E3/DS3/STS-1 1CH 52TQFP
XRT75VL00IV-F IC LIU E3/DS3/STS-1 1CH 52TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R06ES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R06IB 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R06IB208 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Parallel 217-Pin BGA
XRT75R06IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12 制造商:EXAR 制造商全稱:EXAR 功能描述:TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*