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| 型號(hào)： | XRT74L74 |
| 廠商： | Exar Corporation |
| 英文描述： | 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER |
| 中文描述： | 4通道，自動(dòng)取款機(jī)統(tǒng)一/平價(jià)DS3/E3，界定控制器 |
| 文件頁(yè)數(shù)： | 6/498頁(yè) |
| 文件大?。?/td> | 2941K |
| 代理商： | XRT74L74 |
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XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
IV
URE
THE
XRT74L74
TO
TRANSMIT
A
Y
ELLOW
A
LARM
TO
THE
REMOTE
TERMINAL
EQUIPMENT
................................................ 218
T
ABLE
38: D
ESCRIPTION
OF
M
ETHOD
2 T
RANSMIT
O
VERHEAD
I
NPUT
I
NTERFACE
S
IGNALS
................................................................... 219
F
IGURE
66. I
LLUSTRATION
OF
THE
T
ERMINAL
E
QUIPMENT
BEING
INTERFACED
TO
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
(M
ETHOD
2)....................................................................................................................................................................................... 220
T
ABLE
39: T
HE
R
ELATIONSHIP
BETWEEN
THE
N
UMBER
OF
T
X
OHE
NABLE
PULSES
(
SINCE
THE
LAST
OCCURRENCE
OF
THE
T
X
OHF
RAME
PULSE
)
TO
THE
DS3 O
VERHEAD
B
IT
,
THAT
IS
BEING
PROCESSED
BY
THE
XRT74L74........................................................................ 221
F
IGURE
67. B
EHAVIOR
OF
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
SIGNALS
BETWEEN
THE
XRT74L74
AND
THE
T
ERMINAL
E
QUIPMENT
(
FOR
M
ETHOD
2)................................................................................................................................................................. 223
5.2.3 THE TRANSMIT DS3 HDLC CONTROLLER ........................................................................................................... 223
T
X
DS3 FEAC R
EGISTER
(A
DDRESS
= 0
X
32)............................................................................................................224
T
RANSMIT
DS3 FEAC C
ONFIGURATION
AND
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
31) ...................................................224
T
RANSMIT
DS3 FEAC C
ONFIGURATION
AND
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
31) ...................................................224
F
IGURE
68. A F
LOW
C
HART
DEPICTING
HOW
TO
TRANSMIT
A
FEAC M
ESSAGE
VIA
THE
FEAC T
RANSMITTER
........................................ 225
F
IGURE
69. LAPD M
ESSAGE
F
RAME
F
ORMAT
..................................................................................................................................... 226
T
ABLE
40: T
HE
LAPD M
ESSAGE
T
YPE
AND
THE
C
ORRESPONDING
VALUE
OF
THE
F
IRST
B
YTE
,
WITHIN
THE
I
NFORMATION
P
AYLOAD
...... 226
T
RANSMIT
DS3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) .......................................................................227
T
ABLE
41: R
ELATIONSHIP
BETWEEN
T
X
LAPD M
SG
L
ENGTH
AND
THE
LAPD M
ESSAGE
S
IZE
................................................................ 227
T
RANSMIT
DS3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) .......................................................................227
T
ABLE
42: R
ELATIONSHIP
BETWEEN
T
X
LAPD M
SG
L
ENGTH
AND
THE
LAPD M
ESSAGE
S
IZE
................................................................ 227
T
RANSMIT
DS3 LAPD S
TATUS
/I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34)...................................................................228
F
IGURE
70. F
LOW
C
HART
DEPICT
HOW
TO
USE
THE
LAPD T
RANSMITTER
............................................................................................ 229
F
RAMER
O
PERATING
M
ODE
R
EGISTER
(A
DDRESS
= 0
X
00) .........................................................................................230
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
04)..........................................................................................230
5.2.4 THE TRANSMIT DS3 FRAMER BLOCK.................................................................................................................. 230
F
IGURE
71. A S
IMPLE
I
LLUSTRATION
OF
THE
T
RANSMIT
DS3 F
RAMER
B
LOCK
AND
THE
ASSOCIATED
PATHS
TO
OTHER
F
UNCTIONAL
B
LOCKS
231
T
X
DS3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30).............................................................................................232
T
ABLE
43: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
7 (T
X
Y
ELLOW
A
LARM
)
WITHIN
THE
T
X
DS3 C
ONFIGURATION
R
EGISTER
,
AND
THE
RESULTING
T
RANSMIT
DS3 F
RAMER
B
LOCK
’
S
A
CTION
................................................................................................... 232
T
ABLE
44: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
6 (T
X
X-B
ITS
)
WITHIN
THE
T
X
DS3 C
ONFIGURATION
R
EGISTER
,
AND
THE
RE
-
SULTING
T
RANSMIT
DS3 F
RAMER
B
LOCK
’
S
A
CTION
.............................................................................................................. 232
T
ABLE
45: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
5 (T
X
I
DLE
)
WITHIN
THE
T
X
DS3 C
ONFIGURATION
R
EGISTER
,
AND
THE
RESULT
-
ING
T
RANSMIT
DS3 F
RAMER
A
CTION
................................................................................................................................... 233
T
ABLE
46: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
4 (T
X
AIS P
ATTERN
)
WITHIN
THE
T
X
DS3 C
ONFIGURATION
R
EGISTER
,
AND
THE
RESULTING
T
RANSMIT
DS3 F
RAMER
B
LOCK
’
S
A
CTION
.......................................................................................................... 233
T
ABLE
47: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
3 (T
X
LOS)
WITHIN
THE
T
X
DS3 C
ONFIGURATION
R
EGISTER
,
AND
THE
RESULT
-
ING
T
RANSMIT
DS3 F
RAMER
B
LOCK
’
S
A
CTION
..................................................................................................................... 234
T
X
DS3 M-B
IT
M
ASK
R
EGISTER
, A
DDRESS
= 0
X
35....................................................................................................234
T
X
DS3 F-B
IT
M
ASK
1 R
EGISTER
, A
DDRESS
= 0
X
36...................................................................................................235
T
X
DS3 F-B
IT
M
ASK
2 R
EGISTER
, A
DDRESS
= 0
X
37...................................................................................................235
T
X
DS3 F-B
IT
M
ASK
3 R
EGISTER
, A
DDRESS
= 0
X
38...................................................................................................235
T
X
DS3 F-B
IT
M
ASK
4 R
EGISTER
, A
DDRESS
= 0
X
39...................................................................................................235
5.2.5 THE TRANSMIT DS3 LINE INTERFACE BLOCK.................................................................................................... 235
F
IGURE
72. A
PPROACH
TO
I
NTERFACING
THE
XRT74L74 F
RAMER
IC
TO
THE
XRT73L00 DS3/E3/STS-1 T
RANSMITTER
LIU (
ONE
CHANNEL
SHOWN
).............................................................................................................................................................................. 236
F
IGURE
73. A S
IMPLE
I
LLUSTRATION
OF
THE
T
RANSMIT
DS3 LIU I
NTERFACE
BLOCK
............................................................................ 237
F
IGURE
74. T
HE
B
EHAVIOR
OF
T
X
POS
AND
T
X
NEG
SIGNALS
DURING
DATA
TRANSMISSION
WHILE
THE
T
RANSMIT
DS3 LIU I
NTERFACE
IS
OP
-
ERATING
IN
THE
U
NIPOLAR
M
ODE
........................................................................................................................................ 237
I/O C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
01) ..............................................................................................................238
T
ABLE
48: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENT
OF
B
IT
3 (U
NIPOLAR
/B
IPOLAR
*)
WITHIN
THE
UNI I/O C
ONTROL
R
EGISTER
AND
THE
T
RANSMIT
DS3 F
RAMER
L
INE
I
NTERFACE
O
UTPUT
M
ODE
.................................................................................................... 238
F
IGURE
75. I
LLUSTRATION
OF
AMI L
INE
C
ODE
.................................................................................................................................... 239
F
IGURE
76. I
LLUSTRATION
OF
TWO
EXAMPLES
OF
B3ZS E
NCODING
..................................................................................................... 239
I/O C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
01) ..............................................................................................................240
T
ABLE
49: T
HE
R
ELATIONSHIP
BETWEEN
B
IT
4 (AMI/B3ZS*)
WITHIN
THE
I/O C
ONTROL
R
EGISTER
AND
THE
B
IPOLAR
L
INE
C
ODE
THAT
IS
OUTPUT
BY
THE
T
RANSMIT
DS3 LIU I
NTERFACE
B
LOCK
.................................................................................................................... 240
II/O C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
01) .............................................................................................................240
T
ABLE
50: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
2 (T
X
L
INE
C
LK
I
NV
)
WITHIN
THE
I/O C
ONTROL
R
EGISTER
AND
THE
T
X
L
INE
C
LK
CLOCK
EDGE
THAT
T
X
POS
AND
T
X
NEG
ARE
UPDATED
ON
................................................................................................... 240
F
IGURE
77. W
AVEFORM
/T
IMING
R
ELATIONSHIP
BETWEEN
T
X
L
INE
C
LK
, T
X
POS
AND
T
X
NEG - T
X
POS
AND
T
X
NEG
ARE
CONFIGURED
TO
BE
UPDATED
ON
THE
RISING
EDGE
OF
T
X
L
INE
C
LK
..................................................................................................................... 241
F
IGURE
78. W
AVEFORM
/T
IMING
R
ELATIONSHIP
BETWEEN
T
X
L
INE
C
LK
, T
X
POS
AND
T
X
NEG - T
X
POS
AND
T
X
NEG
ARE
CONFIGURED
TO
BE
UPDATED
ON
THE
FALLING
EDGE
OF
T
X
L
INE
C
LK
................................................................................................................... 241
5.2.6 TRANSMIT SECTION INTERRUPT PROCESSING................................................................................................. 241
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