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參數(shù)資料
| 型號(hào)： | XRT73R12IB |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 27/89頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT73R12
30
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
4.4
TRANSMIT PULSE SHAPER
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark
Inversion (AMI) pulse that meets the industry standard mask template requirements for STS-1 and DS3. For
E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped
pulse with very little slope. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can
either be disabled or enabled by setting the TxLEV_n bit to “1” or “0” in the control register. For DS3/STS-1
rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse
template requirements are met at the Cross-Connect system. The distance between the transmitter output and
the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is
measured at the secondary of the transformer and since there is no Cross-Connect system pulse template
requirements, the Transmit Build Out Circuit is always disabled. The differential line driver increases the
transmit waveform to appropriate level and drives into the 75
load as shown in Figure 20.
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT
4.4.1
Guidelines for using Transmit Build Out Circuit
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet,
enable the Transmit Build Out Circuit by setting the TxLEV_n control bit to “0”. If the distance between the
transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit.
FIGURE 19. HDB3 ENCODING FORMAT
0
1
V
B
V
1
0
V
0
TClk
Line
Signal
TPDATA
TTIP(n)
TRing(n)
1:1
R3
75
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TPData(n)
TNData(n)
TxClk(n)
31.6
+ 1%
31.6
+1%
R1
R2
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| XRT73R12IB-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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