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參數(shù)資料
| 型號： | XRT73R12IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 18/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT73R12
22
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
3.3.1
Recommendations for Equalizer Settings
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be enabled. However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses
(that does not meet the pulse template requirements), it is recommended that the Equalizer be disabled for
cable length less than 300 feet. This would help to prevent over-equalization of the signal and thus optimize
the performance in terms of better jitter transfer characteristics. The Equalizer also contains an additional 20
dB gain stage to provide the line monitoring capability (Receive Monitor Mode) of the resistively attenuated
signals which may have 20dB flat loss. The equalizer and the equalizer gain mode can be enabled by
programming the appropriate register. However, enabling the equalizer gain mode (Receive Monitor Mode)
suppresses the internal LOS circuitry and LOS will never assert nor LOS be declared when operating with
Receive Monitor Mode enabled.
NOTE: The results of extensive testing indicate that even when the Equalizer was enabled, regardless of the cable length,
the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
3.4
Clock and Data Recovery
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream
and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the
following two modes:
3.4.1
Data/Clock Recovery Mode
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
3.4.2
Training Mode
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of
Lock condition is declared by toggling RLOL_n output pin “High” or setting the RLOL_n bit to “1” in the control
register. Also, the clock output on the RxClk_n pins are the same as the reference channel clock.
3.5
LOS (Loss of Signal) Detector
3.5.1
DS3/STS-1 LOS Condition
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses. Analog Loss of
Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown
in the Table 3.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the
logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled
“High” and the RLOS_n bit is set to “1” in the status control register.
FIGURE 7. ACG/EQUALIZER BLOCK DIAGRAM
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
RTIP_n
RRing_n
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| XRT73R12IB-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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