參數(shù)資料
型號(hào)： XRT73R12IB
廠商： Exar Corporation
文件頁(yè)數(shù)： 1/89頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
OCTOBER 2007
REV. 1.0.3
GENERAL DESCRIPTION
The XRT73R12 is a twelve channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
for E3/DS3/STS-1 applications. The LIU incorporates
12 independent Receivers and Transmitters in a
single 420 Lead TBGA package.
Each
channel
of
the
XRT73R12
can
be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT73R12’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT73R12 provides a Parallel Microprocessor
Interface for programming and control.
The XRT73R12 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
E3/DS3 Access Equipment
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73R12
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT73R12IB
420 Lead TBGA
-40°C to +85°C
XRT73R12
Channel 11
Channel 0
Channel n...
Device
Monitor
MTIP_n
MRing_n
DMO_n
Timing
Control
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
Tx
Control
MUX
Line
Driver
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Processor Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
RD
WR
Addr[7:0]
CS
INT
D[7:0]
TxON
TxClk_n
TxPOS_n
TxNEG_n
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
RLOL_n
RTIP_n
RRing_n
TTIP_n
TRing_n
CLKOUT_n
SFM_en
E3Clk
DS3Clk
STS-Clk/12M
ICT
Pmode
RDY
PCLK
RESET
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