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參數(shù)資料
| 型號： | XRT73R12IB-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 17/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT73R12
21
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.3
3.0
THE RECEIVER SECTION
The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by
cable loss or flat loss according to industry specifications.
Once data is recovered, it is processed and
presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC.
This section describes the detailed operation of various blocks within the receive path. A simplified block
diagram of the receive path is shown in Figure 5.
3.1
Receive Line Interface
Physical Layer devices are AC coupled to a line interface through a 1:1 transformer. The transformer provides
isolation and a level shift by blocking the DC offset of the incoming data stream. The typical medium for the
line interface is a 75
coxial cable. Whether using E3, DS-3 or STS-1, the LIU requires the same bill of
materials, see Figure 6.
3.2
Adaptive Gain Control (AGC)
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak
detector provides feedback to the equalizer before slicing occurs.
3.3
Receive Equalizer
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of
up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register.
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM
FIGURE 6. RECEIVE LINE INTERFACECONNECTION
Channel n
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Clock & Data
Recovery
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
RTIP_n
RRing_n
DS-3/E3/STS-1
1:1
Receiver
75
RLOS_n
RTIP_n
RRing_n
37.5
0.01
F
37.5
DS-3/E3/STS-1
1:1
Receiver
75
RLOS_n
RTIP_n
RRing_n
37.5
0.01
F
37.5
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